Set Wire_Bend 2;
Grid inch 0.1 1 inch;
Layer 1 Top;
Layer 16 Bottom;
Layer 17 Pads;
Layer 18 Vias;
Layer 19 Unrouted;
Layer 20 Dimension;
Layer 21 tPlace;
Layer 22 bPlace;
Layer 23 tOrigins;
Layer 24 bOrigins;
Layer 25 tNames;
Layer 26 bNames;
Layer 27 tValues;
Layer 28 bValues;
Layer 29 tStop;
Layer 30 bStop;
Layer 31 tCream;
Layer 32 bCream;
Layer 33 tFinish;
Layer 34 bFinish;
Layer 35 tGlue;
Layer 36 bGlue;
Layer 37 tTest;
Layer 38 bTest;
Layer 39 tKeepout;
Layer 40 bKeepout;
Layer 41 tRestrict;
Layer 42 bRestrict;
Layer 43 vRestrict;
Layer 44 Drills;
Layer 45 Holes;
Layer 46 Milling;
Layer 47 Measures;
Layer 48 Document;
Layer 49 Reference;
Layer 91 Nets;
Layer 92 Busses;
Layer 93 Pins;
Layer 94 Symbols;
Layer 95 Names;
Layer 96 Values;
Edit 65C22.sym;
Layer 94;
Wire 0.01 (-0.4 1.1) (0.4 1.1) (0.4 -1.2) (-0.4 -1.2) \
(-0.4 1.1);
Pin 'PA0' I/O None Middle R0 Both 0 (-0.6 1);
Pin 'PA1' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'PA2' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'PA3' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'PA4' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'PA5' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'PA6' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'PA7' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'PB0' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'PB1' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'PB2' I/O None Middle R0 Both 0 (-0.6 -0.1);
Pin 'PB3' I/O None Middle R0 Both 0 (-0.6 -0.2);
Pin 'PB4' I/O None Middle R0 Both 0 (-0.6 -0.3);
Pin 'PB5' I/O None Middle R0 Both 0 (-0.6 -0.4);
Pin 'PB6' I/O None Middle R0 Both 0 (-0.6 -0.5);
Pin 'PB7' I/O None Middle R0 Both 0 (-0.6 -0.6);
Pin 'CA1' I/O None Middle R0 Both 0 (-0.6 -0.8);
Pin 'CA2' I/O None Middle R0 Both 0 (-0.6 -0.9);
Pin 'CB1' I/O None Middle R0 Both 0 (-0.6 -1);
Pin 'CB2' I/O None Middle R0 Both 0 (-0.6 -1.1);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -1);
Pin 'RS0' In None Middle R180 Both 0 (0.6 0.1);
Pin 'RS1' In None Middle R180 Both 0 (0.6 0);
Pin 'RS2' In None Middle R180 Both 0 (0.6 -0.1);
Pin 'RS3' In None Middle R180 Both 0 (0.6 -0.2);
Pin 'RESB' In Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 1);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'CS1' In None Middle R180 Both 0 (0.6 -0.8);
Pin 'CS2B' In Dot Middle R180 Both 0 (0.6 -0.7);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -0.6);
Pin 'IRQB' Out Dot Middle R180 Both 0 (0.6 -0.5);
Layer 95;
Change Size 0.08;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.08;
Change Ratio 8;
Text '6522' R0 (-0.4 -1.3);
Edit 6526.sym;
Layer 94;
Wire 0.01 (-0.4 1.1) (0.4 1.1) (0.4 -1.2) (-0.4 -1.2) \
(-0.4 1.1);
Pin 'PA0' I/O None Middle R0 Both 0 (-0.6 1);
Pin 'PA1' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'PA2' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'PA3' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'PA4' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'PA5' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'PA6' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'PA7' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'PB0' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'PB1' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'PB2' I/O None Middle R0 Both 0 (-0.6 -0.1);
Pin 'PB3' I/O None Middle R0 Both 0 (-0.6 -0.2);
Pin 'PB4' I/O None Middle R0 Both 0 (-0.6 -0.3);
Pin 'PB5' I/O None Middle R0 Both 0 (-0.6 -0.4);
Pin 'PB6' I/O None Middle R0 Both 0 (-0.6 -0.5);
Pin 'PB7' I/O None Middle R0 Both 0 (-0.6 -0.6);
Pin 'RS0' In None Middle R0 Both 0 (-0.6 -0.8);
Pin 'RS1' In None Middle R0 Both 0 (-0.6 -0.9);
Pin 'RS2' In None Middle R0 Both 0 (-0.6 -1);
Pin 'RS3' In None Middle R0 Both 0 (-0.6 -1.1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 1);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'PCB' Out Dot Middle R180 Both 0 (0.6 0.1);
Pin 'FLAGB' In Dot Middle R180 Both 0 (0.6 0);
Pin 'TOD' In None Middle R180 Both 0 (0.6 -0.1);
Pin 'CNT' I/O None Middle R180 Both 0 (0.6 -0.2);
Pin 'SP' I/O None Middle R180 Both 0 (0.6 -0.3);
Pin 'IRQB' Out Dot Middle R180 Both 0 (0.6 -0.5);
Pin 'RESB' In Dot Middle R180 Both 0 (0.6 -0.7);
Pin 'CSB' In Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -0.9);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.08;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.08;
Change Ratio 8;
Text '6526' R0 (-0.4 -1.3);
Edit 6532.sym;
Layer 94;
Wire 0.01 (-0.4 1.1) (0.4 1.1) (0.4 -1.2) (-0.4 -1.2) \
(-0.4 1.1);
Pin 'PA0' I/O None Middle R0 Both 0 (-0.6 1);
Pin 'PA1' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'PA2' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'PA3' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'PA4' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'PA5' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'PA6' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'PA7' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'PB0' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'PB1' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'PB2' I/O None Middle R0 Both 0 (-0.6 -0.1);
Pin 'PB3' I/O None Middle R0 Both 0 (-0.6 -0.2);
Pin 'PB4' I/O None Middle R0 Both 0 (-0.6 -0.3);
Pin 'PB5' I/O None Middle R0 Both 0 (-0.6 -0.4);
Pin 'PB6' I/O None Middle R0 Both 0 (-0.6 -0.5);
Pin 'PB7' I/O None Middle R0 Both 0 (-0.6 -0.6);
Pin 'CS1' In None Middle R0 Both 0 (-0.6 -0.8);
Pin 'CS2B' In Dot Middle R0 Both 0 (-0.6 -0.9);
Pin 'RSB' In Dot Middle R0 Both 0 (-0.6 -1);
Pin 'RESB' In Dot Middle R0 Both 0 (-0.6 -1.1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 1);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'A0' In None Middle R180 Both 0 (0.6 0.1);
Pin 'A1' In None Middle R180 Both 0 (0.6 0);
Pin 'A2' In None Middle R180 Both 0 (0.6 -0.1);
Pin 'A3' In None Middle R180 Both 0 (0.6 -0.2);
Pin 'A4' In None Middle R180 Both 0 (0.6 -0.3);
Pin 'A5' In None Middle R180 Both 0 (0.6 -0.4);
Pin 'A6' In None Middle R180 Both 0 (0.6 -0.5);
Pin 'IRQB' Out Dot Middle R180 Both 0 (0.6 -0.7);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -0.9);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.08;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.08;
Change Ratio 8;
Text '6532' R0 (-0.4 -1.3);
Edit 65C51.sym;
Layer 94;
Wire 0.01 (-0.4 1) (0.4 1) (0.4 -1.1) (-0.4 -1.1) \
(-0.4 1);
Pin 'RXCLK' I/O None Middle R180 Both 0 (0.6 0);
Pin 'XTLI' In None Middle R0 Both 0 (-0.6 0.7);
Pin 'XTLO' Out None Middle R0 Both 0 (-0.6 0.6);
Pin 'IRQ' Out Dot Middle R180 Both 0 (0.6 -0.7);
Pin 'PHI2' In Clk Middle R0 Both 0 (-0.6 0.9);
Pin 'RS0' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'RS1' In None Middle R0 Both 0 (-0.6 0);
Pin 'R/W' In Dot Middle R0 Both 0 (-0.6 -0.7);
Pin 'CS0' In None Middle R0 Both 0 (-0.6 -0.9);
Pin 'CS1' In Dot Middle R0 Both 0 (-0.6 -1);
Pin 'DSR' In Dot Middle R0 Both 0 (-0.6 0.3);
Pin 'RXD' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'CTS' In Dot Middle R0 Both 0 (-0.6 0.4);
Pin 'DCD' In Dot Middle R0 Both 0 (-0.6 0.2);
Pin 'TXD' Out None Middle R180 Both 0 (0.6 -0.5);
Pin 'DTR' Out Dot Middle R180 Both 0 (0.6 -0.2);
Pin 'RTS' Out Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'RES' In Dot Middle R0 Both 0 (-0.6 -0.5);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '6551' R0 (-0.4 -1.2);
Edit 65C816.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'A5' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'A6' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'A7' I/O None Middle R0 Both 0 (-0.6 0.2);
Pin 'A8' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'A9' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'A10' I/O None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A11' I/O None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A12' I/O None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A13' I/O None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A14' I/O None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A15' I/O None Middle R0 Both 0 (-0.6 -0.6);
Pin 'NMIB' In Dot Middle R0 Both 0 (-0.6 -0.8);
Pin 'IRQB' In Dot Middle R0 Both 0 (-0.6 -0.9);
Pin 'BE' In None Middle R0 Both 0 (-0.6 -1);
Pin 'D0/BA0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1/BA1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2/BA2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3/BA3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4/BA4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5/BA5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6/BA6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7/BA7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'PHI2-IN' In Clk Middle R180 Both 0 (0.6 0);
Pin 'E' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'RDY' I/O None Middle R180 Both 0 (0.6 -0.2);
Pin 'MLB' Out Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'M/X' Out None Middle R180 Both 0 (0.6 -0.4);
Pin 'ABORTB' In Dot Middle R180 Both 0 (0.6 -0.5);
Pin 'VPB' Out Dot Middle R180 Both 0 (0.6 -0.6);
Pin 'VPA' Out None Middle R180 Both 0 (0.6 -0.7);
Pin 'VDA' Out None Middle R180 Both 0 (0.6 -0.8);
Pin 'R/WB' Out Dot Middle R180 Both 0 (0.6 -0.9);
Pin 'RESB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '65816' R0 (-0.4 -1.2);
Edit 27128.sym;
Layer 94;
Wire 0.01 (0.4 0.7) (0.4 -0.8) (-0.4 -0.8) (-0.4 0.7) \
(0.4 0.7);
Pin 'A0' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'A5' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A6' In None Middle R0 Both 0 (-0.6 0);
Pin 'A7' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A8' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A9' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A10' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A11' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A12' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'A13' In None Middle R0 Both 0 (-0.6 -0.7);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.1);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 -0.1);
Pin 'BEB' In Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'CEB' In Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'PGM' In None Middle R180 Both 0 (0.6 -0.5);
Pin 'VPP' Pwr None Middle R180 Both 0 (0.6 -0.6);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.7);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '27128' R0 (-0.4 -0.9);
Edit BASROM.sym;
Layer 94;
Wire 0.01 (0.4 0.6) (0.4 -0.7) (-0.4 -0.7) (-0.4 0.6) \
(0.4 0.6);
Pin 'A0' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A5' In None Middle R0 Both 0 (-0.6 0);
Pin 'A6' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A7' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A8' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A9' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A10' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A11' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.1);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 -0.1);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 -0.2);
Pin 'CSB' In Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'A12' In None Middle R180 Both 0 (0.6 -0.6);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.6);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'BASROM' R0 (-0.4 -0.8);
Edit CO61818.sym;
Layer 94;
Wire 0.01 (0.4 0.5) (0.4 -0.6) (-0.4 -0.6) (-0.4 0.5) \
(0.4 0.5);
Pin 'A11' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A12' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A13' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'A14' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A15' In None Middle R0 Both 0 (-0.6 0);
Pin 'MAPB' In Dot Middle R0 Both 0 (-0.6 -0.2);
Pin 'RD4' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'RD5' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'REN' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'S4B' Out Dot Middle R180 Both 0 (0.6 0.4);
Pin 'S5B' Out Dot Middle R180 Both 0 (0.6 0.3);
Pin 'BASB' Out Dot Middle R180 Both 0 (0.6 0.2);
Pin 'OSB' Out Dot Middle R180 Both 0 (0.6 0.1);
Pin 'CIB' Out Dot Middle R180 Both 0 (0.6 0);
Pin 'IOB' Out Dot Middle R180 Both 0 (0.6 -0.1);
Pin 'BEB' In Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'MPDB' In Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'REFB' In Dot Middle R180 Both 0 (0.6 -0.5);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.5);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'CO61818' R0 (-0.4 -0.7);
Edit SALLYCHP.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' Out None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' Out None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' Out None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' Out None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' Out None Middle R0 Both 0 (-0.6 0.5);
Pin 'A5' Out None Middle R0 Both 0 (-0.6 0.4);
Pin 'A6' Out None Middle R0 Both 0 (-0.6 0.3);
Pin 'A7' Out None Middle R0 Both 0 (-0.6 0.2);
Pin 'A8' Out None Middle R0 Both 0 (-0.6 0.1);
Pin 'A9' Out None Middle R0 Both 0 (-0.6 0);
Pin 'A10' Out None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A11' Out None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A12' Out None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A13' Out None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A14' Out None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A15' Out None Middle R0 Both 0 (-0.6 -0.6);
Pin 'NMIB' In None Middle R0 Both 0 (-0.6 -0.8);
Pin 'IRQB' In None Middle R0 Both 0 (-0.6 -0.9);
Pin 'RESB' In Dot Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'PHI2-IN' In Clk Middle R180 Both 0 (0.6 0);
Pin 'PHI2' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'PHI1' Out None Middle R180 Both 0 (0.6 -0.2);
Pin 'HALTB' In Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'NC1' NC None Middle R180 Both 0 (0.6 -0.4);
Pin 'NC2' NC None Middle R180 Both 0 (0.6 -0.5);
Pin 'RDY' I/O None Middle R180 Both 0 (0.6 -0.7);
Pin 'SYNC' Out None Middle R180 Both 0 (0.6 -0.8);
Pin 'SOB' I/O Dot Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' Out Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'Sally (6502)' R0 (-0.4 -1.2);
Edit SALLYSCK.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' In None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'A5' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A6' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A7' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'A8' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A9' In None Middle R0 Both 0 (-0.6 0);
Pin 'A10' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A11' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A12' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A13' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A14' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A15' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'NMIB' Out None Middle R0 Both 0 (-0.6 -0.8);
Pin 'IRQB' Out None Middle R0 Both 0 (-0.6 -0.9);
Pin 'RESB' I/O Dot Middle R0 Both 0 (-0.6 -1);
Pin 'VCC' Out None Middle R90 Both 0 (0 -1.3);
Pin 'GND1' Out None Middle R270 Both 0 (-0.1 1.2);
Pin 'GND2' Out None Middle R270 Both 0 (0.1 1.2);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'PHI2-IN' Out Clk Middle R180 Both 0 (0.6 0);
Pin 'PHI2' In None Middle R180 Both 0 (0.6 -0.1);
Pin 'PHI1' In None Middle R180 Both 0 (0.6 -0.2);
Pin 'HALTB' Out Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'NC1' NC None Middle R180 Both 0 (0.6 -0.4);
Pin 'NC2' NC None Middle R180 Both 0 (0.6 -0.5);
Pin 'RDY' I/O None Middle R180 Both 0 (0.6 -0.7);
Pin 'SYNC' In None Middle R180 Both 0 (0.6 -0.8);
Pin 'SOB' I/O Dot Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'Sally (socket)' R0 (-0.4 -1.2);
Edit 6520.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'PA0' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'PA1' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'PA2' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'PA3' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'PA4' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'PA5' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'PA6' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'PA7' I/O None Middle R0 Both 0 (-0.6 0.2);
Pin 'CA1' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'CA2' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'PB0' I/O None Middle R0 Both 0 (-0.6 -0.1);
Pin 'PB1' I/O None Middle R0 Both 0 (-0.6 -0.2);
Pin 'PB2' I/O None Middle R0 Both 0 (-0.6 -0.3);
Pin 'PB3' I/O None Middle R0 Both 0 (-0.6 -0.4);
Pin 'PB4' I/O None Middle R0 Both 0 (-0.6 -0.5);
Pin 'PB5' I/O None Middle R0 Both 0 (-0.6 -0.6);
Pin 'PB6' I/O None Middle R0 Both 0 (-0.6 -0.7);
Pin 'PB7' I/O None Middle R0 Both 0 (-0.6 -0.8);
Pin 'CB1' I/O None Middle R0 Both 0 (-0.6 -0.9);
Pin 'CB2' I/O None Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'A0' Out None Middle R180 Both 0 (0.6 0);
Pin 'A1' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'IRQAB' Out Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'IRQBB' Out Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'RESB' In Dot Middle R180 Both 0 (0.6 -0.5);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -0.6);
Pin 'CS1' In None Middle R180 Both 0 (0.6 -0.7);
Pin 'CS2B' In Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'CS0' In None Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '6520' R0 (-0.4 -1.2);
Edit POKEY.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'P0' In None Middle R0 Both 0 (-0.6 0.9);
Pin 'P1' In None Middle R0 Both 0 (-0.6 0.8);
Pin 'P2' In None Middle R0 Both 0 (-0.6 0.7);
Pin 'P3' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'P4' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'P5' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'P6' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'P7' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'KR1B' Out Dot Middle R0 Both 0 (-0.6 0);
Pin 'KR2B' Out Dot Middle R0 Both 0 (-0.6 -0.1);
Pin 'K0B' In Dot Middle R0 Both 0 (-0.6 -0.2);
Pin 'K1B' In Dot Middle R0 Both 0 (-0.6 -0.3);
Pin 'K2B' In Dot Middle R0 Both 0 (-0.6 -0.4);
Pin 'K3B' In Dot Middle R0 Both 0 (-0.6 -0.5);
Pin 'K4B' In Dot Middle R0 Both 0 (-0.6 -0.6);
Pin 'K5B' In Dot Middle R0 Both 0 (-0.6 -0.7);
Pin 'CS0B' In None Middle R0 Both 0 (-0.6 -0.9);
Pin 'CS1' In None Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'A0' I/O None Middle R180 Both 0 (0.6 0.1);
Pin 'A1' I/O None Middle R180 Both 0 (0.6 0);
Pin 'A2' I/O None Middle R180 Both 0 (0.6 -0.1);
Pin 'A3' I/O None Middle R180 Both 0 (0.6 -0.2);
Pin 'AUD' Out None Middle R180 Both 0 (0.6 -0.3);
Pin 'SID' In None Middle R180 Both 0 (0.6 -0.4);
Pin 'SOD' Out None Middle R180 Both 0 (0.6 -0.5);
Pin 'ACLK' Out Clk Middle R180 Both 0 (0.6 -0.6);
Pin 'BCLK' I/O Clk Middle R180 Both 0 (0.6 -0.7);
Pin 'IRQB' Out Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'POKEY' R0 (-0.4 -1.2);
Edit ANTIC.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' Out None Middle R0 Both 0 (-0.6 0.5);
Pin 'A5' Out None Middle R0 Both 0 (-0.6 0.4);
Pin 'A6' Out None Middle R0 Both 0 (-0.6 0.3);
Pin 'A7' Out None Middle R0 Both 0 (-0.6 0.2);
Pin 'A8' Out None Middle R0 Both 0 (-0.6 0.1);
Pin 'A9' Out None Middle R0 Both 0 (-0.6 0);
Pin 'A10' Out None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A11' Out None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A12' Out None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A13' Out None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A14' Out None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A15' Out None Middle R0 Both 0 (-0.6 -0.6);
Pin 'RNMIB' Out Dot Middle R0 Both 0 (-0.6 -0.7);
Pin 'NMIB' Out Dot Middle R0 Both 0 (-0.6 -0.8);
Pin 'HALTB' Out Dot Middle R0 Both 0 (-0.6 -0.9);
Pin 'RESB' In Dot Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'AN0' Out None Middle R180 Both 0 (0.6 0);
Pin 'AN1' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'AN2' Out None Middle R180 Both 0 (0.6 -0.2);
Pin 'FPHI0' In Clk Middle R180 Both 0 (0.6 -0.3);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -0.4);
Pin 'PHI0' Out Clk Middle R180 Both 0 (0.6 -0.5);
Pin 'RDY' Out None Middle R180 Both 0 (0.6 -0.6);
Pin 'REFB' Out Dot Middle R180 Both 0 (0.6 -0.7);
Pin 'R/WB' Out Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'LPB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'ANTIC' R0 (-0.4 -1.2);
Edit GTIA.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' In None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'T0' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'T1' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'T2' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'T3' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'S0' In None Middle R0 Both 0 (-0.6 0);
Pin 'S1' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'S2' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'S3' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'AN0' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'AN1' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'AN2' In None Middle R0 Both 0 (-0.6 -0.7);
Pin 'OSC' In Clk Middle R0 Both 0 (-0.6 -0.8);
Pin 'FPHI0' Out Clk Middle R0 Both 0 (-0.6 -0.9);
Pin 'PHI2' In Clk Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'LUM0' Out None Middle R180 Both 0 (0.6 0);
Pin 'LUM1' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'LUM2' Out None Middle R180 Both 0 (0.6 -0.2);
Pin 'LUM3' Out None Middle R180 Both 0 (0.6 -0.3);
Pin 'COLOR' Out None Middle R180 Both 0 (0.6 -0.4);
Pin 'CSYNC' Out None Middle R180 Both 0 (0.6 -0.5);
Pin 'CAD3' In None Middle R180 Both 0 (0.6 -0.6);
Pin 'CSB' In Dot Middle R180 Both 0 (0.6 -0.7);
Pin 'HALTB' In Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'PAL' In Clk Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' Out Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'GTIA' R0 (-0.4 -1.2);
Edit AY-3-8910.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'DA0' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'DA1' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'DA2' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'DA3' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'DA4' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'DA5' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'DA6' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'DA7' I/O None Middle R0 Both 0 (-0.6 0.2);
Pin 'A8' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A9' In Dot Middle R0 Both 0 (-0.6 0);
Pin 'BC1' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'BC2' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'BDIR' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'RESET' In Dot Middle R0 Both 0 (-0.6 -0.4);
Pin 'CLOCK' In Clk Middle R0 Both 0 (-0.6 -0.5);
Pin 'NC1' NC None Middle R0 Both 0 (-0.6 -0.7);
Pin 'NC2' NC None Middle R0 Both 0 (-0.6 -0.8);
Pin 'TEST1' NC None Middle R0 Both 0 (-0.6 -0.9);
Pin 'TEST2' NC None Middle R0 Both 0 (-0.6 -1.0);
Pin 'ChA' Out None Middle R180 Both 0 (0.6 0.9);
Pin 'ChB' Out None Middle R180 Both 0 (0.6 0.8);
Pin 'ChC' Out None Middle R180 Both 0 (0.6 0.7);
Pin 'IOA0' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'IOA1' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'IOA2' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'IOA3' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'IOA4' I/O None Middle R180 Both 0 (0.6 0.1);
Pin 'IOA5' I/O None Middle R180 Both 0 (0.6 0);
Pin 'IOA6' I/O None Middle R180 Both 0 (0.6 -0.1);
Pin 'IOA7' I/O None Middle R180 Both 0 (0.6 -0.2);
Pin 'IOB0' I/O None Middle R180 Both 0 (0.6 -0.3);
Pin 'IOB1' I/O None Middle R180 Both 0 (0.6 -0.4);
Pin 'IOB2' I/O None Middle R180 Both 0 (0.6 -0.5);
Pin 'IOB3' I/O None Middle R180 Both 0 (0.6 -0.6);
Pin 'IOB4' I/O None Middle R180 Both 0 (0.6 -0.7);
Pin 'IOB5' I/O None Middle R180 Both 0 (0.6 -0.8);
Pin 'IOB6' I/O None Middle R180 Both 0 (0.6 -0.9);
Pin 'IOB7' I/O None Middle R180 Both 0 (0.6 -1.0);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'AY-3-8910' R0 (-0.4 -1.2);
Edit AY-3-8912.sym;
Layer 94;
Wire 0.01 (0.4 0.8) (0.4 -0.9) (-0.4 -0.9) (-0.4 0.8) \
(0.4 0.8);
Pin 'DA0' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'DA1' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'DA2' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'DA3' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'DA4' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'DA5' I/O None Middle R0 Both 0 (-0.6 0.2);
Pin 'DA6' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'DA7' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'A8' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'BC1' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'BC2' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'BDIR' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'RESET' In Dot Middle R0 Both 0 (-0.6 -0.5);
Pin 'CLOCK' In Clk Middle R0 Both 0 (-0.6 -0.6);
Pin 'TEST1' NC None Middle R0 Both 0 (-0.6 -0.8);
Pin 'ChA' Out None Middle R180 Both 0 (0.6 0.7);
Pin 'ChB' Out None Middle R180 Both 0 (0.6 0.6);
Pin 'ChC' Out None Middle R180 Both 0 (0.6 0.5);
Pin 'IOA0' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'IOA1' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'IOA2' I/O None Middle R180 Both 0 (0.6 0.1);
Pin 'IOA3' I/O None Middle R180 Both 0 (0.6 0);
Pin 'IOA4' I/O None Middle R180 Both 0 (0.6 -0.1);
Pin 'IOA5' I/O None Middle R180 Both 0 (0.6 -0.2);
Pin 'IOA6' I/O None Middle R180 Both 0 (0.6 -0.3);
Pin 'IOA7' I/O None Middle R180 Both 0 (0.6 -0.4);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.8);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'AY-3-8912' R0 (-0.4 -1);
Edit AY-3-8913.sym;
Layer 94;
Wire 0.01 (0.4 0.8) (0.4 -0.8) (-0.4 -0.8) (-0.4 0.8) \
(0.4 0.8);
Pin 'DA0' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'DA1' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'DA2' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'DA3' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'DA4' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'DA5' I/O None Middle R0 Both 0 (-0.6 0.2);
Pin 'DA6' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'DA7' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'A8' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A9' In Dot Middle R0 Both 0 (-0.6 -0.2);
Pin 'BC1' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'BDIR' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'RESET' In Dot Middle R0 Both 0 (-0.6 -0.5);
Pin 'CLOCK' In Clk Middle R0 Both 0 (-0.6 -0.6);
Pin 'CS' In Dot Middle R0 Both 0 (-0.6 -0.7);
Pin 'ChA' Out None Middle R180 Both 0 (0.6 0.7);
Pin 'ChB' Out None Middle R180 Both 0 (0.6 0.6);
Pin 'ChC' Out None Middle R180 Both 0 (0.6 0.5);
Pin 'TESTIN' NC None Middle R180 Both 0 (0.6 -0.2);
Pin 'TESTOUT' NC None Middle R180 Both 0 (0.6 -0.3);
Pin 'NC' NC None Middle R180 Both 0 (0.6 -0.7);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.8);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'AY-3-8913' R0 (-0.4 -0.9);
Edit YM2151.sym;
Layer 94;
Wire 0.01 (0.4 0.8) (0.4 -0.8) (-0.4 -0.8) (-0.4 0.8) \
(0.4 0.8);
Pin 'D0' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'D1' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'D2' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'D3' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'D4' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'D5' I/O None Middle R0 Both 0 (-0.6 0.2);
Pin 'D6' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'D7' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'A0' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'CS' In Dot Middle R0 Both 0 (-0.6 -0.3);
Pin 'WR' In Dot Middle R0 Both 0 (-0.6 -0.4);
Pin 'RD' In Dot Middle R0 Both 0 (-0.6 -0.5);
Pin 'RESET' In Dot Middle R0 Both 0 (-0.6 -0.6);
Pin 'MCLK' In Clk Middle R0 Both 0 (-0.6 -0.7);
Pin 'CT1' Out None Middle R180 Both 0 (0.6 0.7);
Pin 'CT2' Out None Middle R180 Both 0 (0.6 0.6);
Pin 'SO' Out None Middle R180 Both 0 (0.6 0.4);
Pin 'SH1' Out None Middle R180 Both 0 (0.6 0.3);
Pin 'SH2' Out None Middle R180 Both 0 (0.6 0.2);
Pin 'OCLK' Out Clk Middle R180 Both 0 (0.6 0.1);
Pin 'IRQ' Out Dot Middle R180 Both 0 (0.6 -0.1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.8);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'YM2151' R0 (-0.4 -0.9);
Edit YM3012.sym;
Layer 94;
Wire 0.01 (0.4 0.6) (0.4 -0.5) (-0.4 -0.5) (-0.4 0.6) \
(0.4 0.6);
Pin 'CLK' In Clk Middle R0 Both 0 (-0.6 0.5);
Pin 'DATA' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'SH1' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'SH2' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'RESET' In Dot Middle R0 Both 0 (-0.6 0.1);
Pin 'CH1' Out None Middle R180 Both 0 (0.6 0.5);
Pin 'CH2' Out None Middle R180 Both 0 (0.6 0.4);
Pin 'COM' Out None Middle R180 Both 0 (0.6 0.3);
Pin 'TO-BUF' Out None Middle R180 Both 0 (0.6 0.2);
Pin 'V/2' In None Middle R180 Both 0 (0.6 0.1);
Pin 'BIAS+' Out Dot Middle R180 Both 0 (0.6 0);
Pin 'BIAS-' Out Dot Middle R180 Both 0 (0.6 -0.1);
Pin 'A-GND1' Pwr None Middle R180 Both 0 (0.6 -0.3);
Pin 'A-GND2' Pwr None Middle R180 Both 0 (0.6 -0.4);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.6);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'YM3012' R0 (-0.4 -0.6);
Edit CTS256A-AL2.sym;
Layer 94;
Wire 0.01 (0.8 1) (0.8 -1.1) (-0.8 -1.1) (-0.8 1) \
(0.8 1);
Pin 'A0' I/O None Middle R0 Both 0 (-1 0.9);
Pin 'A1' I/O None Middle R0 Both 0 (-1 0.8);
Pin 'A2' I/O None Middle R0 Both 0 (-1 0.7);
Pin 'A3' I/O None Middle R0 Both 0 (-1 0.6);
Pin 'A4' I/O None Middle R0 Both 0 (-1 0.5);
Pin 'A5/RXD' I/O None Middle R0 Both 0 (-1 0.4);
Pin 'A6/SCLK' I/O None Middle R0 Both 0 (-1 0.3);
Pin 'A7' I/O None Middle R0 Both 0 (-1 0.2);
Pin 'B0' I/O None Middle R0 Both 0 (-1 0.1);
Pin 'B1' I/O None Middle R0 Both 0 (-1 0);
Pin 'B2' I/O None Middle R0 Both 0 (-1 -0.1);
Pin 'B3/TXD' I/O None Middle R0 Both 0 (-1 -0.2);
Pin 'B4/ALATCH' I/O None Middle R0 Both 0 (-1 -0.3);
Pin 'B5/R/W' I/O None Middle R0 Both 0 (-1 -0.4);
Pin 'B6/ENABLE' I/O None Middle R0 Both 0 (-1 -0.5);
Pin 'B7/CLOCKOUT' I/O None Middle R0 Both 0 (-1 -0.6);
Pin 'INT1' In None Middle R0 Both 0 (-1 -0.7);
Pin 'INT3' In None Middle R0 Both 0 (-1 -0.8);
Pin 'MC' In None Middle R0 Both 0 (-1 -0.9);
Pin 'RESET' In Dot Middle R0 Both 0 (-1 -1);
Pin 'C0' I/O None Middle R180 Both 0 (1 0.9);
Pin 'C1' I/O None Middle R180 Both 0 (1 0.8);
Pin 'C2' I/O None Middle R180 Both 0 (1 0.7);
Pin 'C3' I/O None Middle R180 Both 0 (1 0.6);
Pin 'C4' I/O None Middle R180 Both 0 (1 0.5);
Pin 'C5' I/O None Middle R180 Both 0 (1 0.4);
Pin 'C6' I/O None Middle R180 Both 0 (1 0.3);
Pin 'C7' I/O None Middle R180 Both 0 (1 0.2);
Pin 'D0' I/O None Middle R180 Both 0 (1 0.1);
Pin 'D1' I/O None Middle R180 Both 0 (1 0);
Pin 'D2' I/O None Middle R180 Both 0 (1 -0.1);
Pin 'D3' I/O None Middle R180 Both 0 (1 -0.2);
Pin 'D4' I/O None Middle R180 Both 0 (1 -0.3);
Pin 'D5' I/O None Middle R180 Both 0 (1 -0.4);
Pin 'D6' I/O None Middle R180 Both 0 (1 -0.5);
Pin 'D7' I/O None Middle R180 Both 0 (1 -0.6);
Pin 'XTAL1' Out None Middle R180 Both 0 (1 -0.8);
Pin 'XTAL2/CLOCKIN' In None Middle R180 Both 0 (1 -0.9);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.8 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'CTS256A-AL2' R0 (-0.8 -1.2);
Edit SP0256.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1) (-0.4 -1) (-0.4 1) \
(0.4 1);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.9);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.8);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.7);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'A5' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'A6' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A7' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A8' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'SE' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'ALD' In Dot Middle R0 Both 0 (-0.6 0);
Pin 'LRQ' Out Dot Middle R0 Both 0 (-0.6 -0.1);
Pin 'SBY' Out None Middle R0 Both 0 (-0.6 -0.3);
Pin 'SBY-RST' In Dot Middle R0 Both 0 (-0.6 -0.4);
Pin 'RST' In Dot Middle R0 Both 0 (-0.6 -0.5);
Pin 'OSC1' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'OSC2' Out None Middle R0 Both 0 (-0.6 -0.7);
Pin 'TEST' In None Middle R0 Both 0 (-0.6 -0.9);
Pin 'SERIN' In None Middle R180 Both 0 (0.6 0.9);
Pin 'SEROUT' In None Middle R180 Both 0 (0.6 0.8);
Pin 'C1' Out None Middle R180 Both 0 (0.6 0.7);
Pin 'C2' Out None Middle R180 Both 0 (0.6 0.6);
Pin 'C3' Out None Middle R180 Both 0 (0.6 0.5);
Pin 'ROMCLK' In None Middle R180 Both 0 (0.6 0.4);
Pin 'ROMDIS' In None Middle R180 Both 0 (0.6 0.3);
Pin 'DIGOUT' In None Middle R180 Both 0 (0.6 0);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'SP0256' R0 (-0.4 -1.1);
Edit P.sym;
Pin 'VCC' Pwr None Middle R270 Off 0 (0 0.3);
Pin 'GND' Pwr None Middle R90 Off 0 (0 -0.3);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'GND' R0 (0.1 -0.5);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'VCC' R0 (0.1 0.4);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (0 0);
Edit P-CMOS.sym;
Pin 'VCC' Pwr None Middle R270 Off 0 (0 0.3);
Pin 'GND' Pwr None Middle R90 Off 0 (0 -0.3);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (0 0);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'VCC' R0 (0.1 0.4);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'GND' R0 (0.1 -0.4);
Edit DIL16.pac;
Description 'SOCKET DIL16';
Change Drill 0.032;Pad '1' Octagon 0 (-0.35 -0.15);
Change Drill 0.032;Pad '2' Octagon 0 (-0.25 -0.15);
Change Drill 0.032;Pad '3' Octagon 0 (-0.15 -0.15);
Change Drill 0.032;Pad '4' Octagon 0 (-0.05 -0.15);
Change Drill 0.032;Pad '5' Octagon 0 (0.05 -0.15);
Change Drill 0.032;Pad '6' Octagon 0 (0.15 -0.15);
Change Drill 0.032;Pad '7' Octagon 0 (0.25 -0.15);
Change Drill 0.032;Pad '8' Octagon 0 (0.35 -0.15);
Change Drill 0.032;Pad '9' Octagon 0 (0.35 0.15);
Change Drill 0.032;Pad '10' Octagon 0 (0.25 0.15);
Change Drill 0.032;Pad '11' Octagon 0 (0.15 0.15);
Change Drill 0.032;Pad '12' Octagon 0 (0.05 0.15);
Change Drill 0.032;Pad '13' Octagon 0 (-0.05 0.15);
Change Drill 0.032;Pad '14' Octagon 0 (-0.15 0.15);
Change Drill 0.032;Pad '15' Octagon 0 (-0.25 0.15);
Change Drill 0.032;Pad '16' Octagon 0 (-0.35 0.15);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R90 (-0.411 -0.105);
Layer 21;
Wire 0.005 (-0.4 -0.025) (-0.4 -0.11);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.33 -0.038);
Layer 21;
Arc CCW 0.005 (-0.4 -0.025) (-0.4 0.025) (-0.4 0.025);
Layer 21;
Wire 0.005 (-0.4 -0.11) (0.4 -0.11) (0.4 0.11) (-0.4 0.11) \
(-0.4 0.025);
Edit DIL20.pac;
Description 'SOCKET DIL20';
Change Drill 0.032;Pad '1' Octagon 0 (-0.45 -0.15);
Change Drill 0.032;Pad '2' Octagon 0 (-0.35 -0.15);
Change Drill 0.032;Pad '3' Octagon 0 (-0.25 -0.15);
Change Drill 0.032;Pad '4' Octagon 0 (-0.15 -0.15);
Change Drill 0.032;Pad '5' Octagon 0 (-0.05 -0.15);
Change Drill 0.032;Pad '6' Octagon 0 (0.05 -0.15);
Change Drill 0.032;Pad '7' Octagon 0 (0.15 -0.15);
Change Drill 0.032;Pad '8' Octagon 0 (0.25 -0.15);
Change Drill 0.032;Pad '9' Octagon 0 (0.35 -0.15);
Change Drill 0.032;Pad '10' Octagon 0 (0.45 -0.15);
Change Drill 0.032;Pad '11' Octagon 0 (0.45 0.15);
Change Drill 0.032;Pad '12' Octagon 0 (0.35 0.15);
Change Drill 0.032;Pad '13' Octagon 0 (0.25 0.15);
Change Drill 0.032;Pad '14' Octagon 0 (0.15 0.15);
Change Drill 0.032;Pad '15' Octagon 0 (0.05 0.15);
Change Drill 0.032;Pad '16' Octagon 0 (-0.05 0.15);
Change Drill 0.032;Pad '17' Octagon 0 (-0.15 0.15);
Change Drill 0.032;Pad '18' Octagon 0 (-0.25 0.15);
Change Drill 0.032;Pad '19' Octagon 0 (-0.35 0.15);
Change Drill 0.032;Pad '20' Octagon 0 (-0.45 0.15);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R90 (-0.507 -0.105);
Layer 21;
Wire 0.005 (-0.495 -0.025) (-0.495 -0.11);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.41 -0.035);
Layer 21;
Arc CCW 0.005 (-0.495 -0.025) (-0.495 0.025) (-0.495 0.025);
Layer 21;
Wire 0.005 (0.495 -0.11) (0.495 0.11);
Wire 0.005 (0.495 -0.11) (-0.495 -0.11);
Wire 0.005 (-0.495 0.11) (-0.495 0.025);
Wire 0.005 (-0.495 0.11) (0.495 0.11);
Edit DIL24-6.pac;
Description 'SOCKET DIL24, 0.6 inch';
Change Drill 0.032;Pad '1' Octagon 0 (-0.55 -0.3);
Change Drill 0.032;Pad '2' Octagon 0 (-0.45 -0.3);
Change Drill 0.032;Pad '3' Octagon 0 (-0.35 -0.3);
Change Drill 0.032;Pad '4' Octagon 0 (-0.25 -0.3);
Change Drill 0.032;Pad '5' Octagon 0 (-0.15 -0.3);
Change Drill 0.032;Pad '6' Octagon 0 (-0.05 -0.3);
Change Drill 0.032;Pad '7' Octagon 0 (0.05 -0.3);
Change Drill 0.032;Pad '8' Octagon 0 (0.15 -0.3);
Change Drill 0.032;Pad '9' Octagon 0 (0.25 -0.3);
Change Drill 0.032;Pad '10' Octagon 0 (0.35 -0.3);
Change Drill 0.032;Pad '11' Octagon 0 (0.45 -0.3);
Change Drill 0.032;Pad '12' Octagon 0 (0.55 -0.3);
Change Drill 0.032;Pad '13' Octagon 0 (0.55 0.3);
Change Drill 0.032;Pad '14' Octagon 0 (0.45 0.3);
Change Drill 0.032;Pad '15' Octagon 0 (0.35 0.3);
Change Drill 0.032;Pad '16' Octagon 0 (0.25 0.3);
Change Drill 0.032;Pad '17' Octagon 0 (0.15 0.3);
Change Drill 0.032;Pad '18' Octagon 0 (0.05 0.3);
Change Drill 0.032;Pad '19' Octagon 0 (-0.05 0.3);
Change Drill 0.032;Pad '20' Octagon 0 (-0.15 0.3);
Change Drill 0.032;Pad '21' Octagon 0 (-0.25 0.3);
Change Drill 0.032;Pad '22' Octagon 0 (-0.35 0.3);
Change Drill 0.032;Pad '23' Octagon 0 (-0.45 0.3);
Change Drill 0.032;Pad '24' Octagon 0 (-0.55 0.3);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R0 (-0.45 0.015);
Layer 21;
Wire 0.005 (-0.595 -0.05) (-0.595 -0.26);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '1' R90 (-0.525 -0.238);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '24' R90 (-0.525 0.162);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '12' R90 (0.575 -0.238);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '13' R90 (0.575 0.162);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.45 -0.085);
Layer 21;
Arc CW 0.005 (-0.595 0.05) (-0.595 -0.05) (-0.595 -0.05);
Layer 21;
Wire 0.005 (0.595 -0.26) (0.595 0.26);
Wire 0.005 (-0.595 0.26) (-0.595 0.05);
Wire 0.005 (-0.595 0.26) (0.595 0.26);
Wire 0.005 (-0.595 -0.26) (0.595 -0.26);
Edit DIL28-6.pac;
Description 'SOCKET DIL28, 0.6 inch';
Change Drill 0.032;Pad '1' Octagon 0 (-0.65 -0.3);
Change Drill 0.032;Pad '2' Octagon 0 (-0.55 -0.3);
Change Drill 0.032;Pad '3' Octagon 0 (-0.45 -0.3);
Change Drill 0.032;Pad '4' Octagon 0 (-0.35 -0.3);
Change Drill 0.032;Pad '5' Octagon 0 (-0.25 -0.3);
Change Drill 0.032;Pad '6' Octagon 0 (-0.15 -0.3);
Change Drill 0.032;Pad '7' Octagon 0 (-0.05 -0.3);
Change Drill 0.032;Pad '8' Octagon 0 (0.05 -0.3);
Change Drill 0.032;Pad '9' Octagon 0 (0.15 -0.3);
Change Drill 0.032;Pad '10' Octagon 0 (0.25 -0.3);
Change Drill 0.032;Pad '11' Octagon 0 (0.35 -0.3);
Change Drill 0.032;Pad '12' Octagon 0 (0.45 -0.3);
Change Drill 0.032;Pad '13' Octagon 0 (0.55 -0.3);
Change Drill 0.032;Pad '14' Octagon 0 (0.65 -0.3);
Change Drill 0.032;Pad '15' Octagon 0 (0.65 0.3);
Change Drill 0.032;Pad '16' Octagon 0 (0.55 0.3);
Change Drill 0.032;Pad '17' Octagon 0 (0.45 0.3);
Change Drill 0.032;Pad '18' Octagon 0 (0.35 0.3);
Change Drill 0.032;Pad '19' Octagon 0 (0.25 0.3);
Change Drill 0.032;Pad '20' Octagon 0 (0.15 0.3);
Change Drill 0.032;Pad '21' Octagon 0 (0.05 0.3);
Change Drill 0.032;Pad '22' Octagon 0 (-0.05 0.3);
Change Drill 0.032;Pad '23' Octagon 0 (-0.15 0.3);
Change Drill 0.032;Pad '24' Octagon 0 (-0.25 0.3);
Change Drill 0.032;Pad '25' Octagon 0 (-0.35 0.3);
Change Drill 0.032;Pad '26' Octagon 0 (-0.45 0.3);
Change Drill 0.032;Pad '27' Octagon 0 (-0.55 0.3);
Change Drill 0.032;Pad '28' Octagon 0 (-0.65 0.3);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R0 (-0.55 0.025);
Layer 21;
Wire 0.005 (-0.695 -0.05) (-0.695 -0.26);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '1' R90 (-0.625 -0.237);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '28' R90 (-0.625 0.151);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '14' R90 (0.675 -0.238);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '15' R90 (0.675 0.162);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.55 -0.087);
Layer 21;
Arc CW 0.005 (-0.695 0.05) (-0.695 -0.05) (-0.695 -0.05);
Layer 21;
Wire 0.005 (0.695 -0.26) (0.695 0.26);
Wire 0.005 (-0.695 0.26) (-0.695 0.05);
Wire 0.005 (-0.695 0.26) (0.695 0.26);
Wire 0.005 (-0.695 -0.26) (0.695 -0.26);
Edit DIL40.pac;
Description 'SOCKET DIL40';
Change Drill 0.032;Pad '1' Octagon 0 (-0.95 -0.3);
Change Drill 0.032;Pad '2' Octagon 0 (-0.85 -0.3);
Change Drill 0.032;Pad '3' Octagon 0 (-0.75 -0.3);
Change Drill 0.032;Pad '4' Octagon 0 (-0.65 -0.3);
Change Drill 0.032;Pad '5' Octagon 0 (-0.55 -0.3);
Change Drill 0.032;Pad '6' Octagon 0 (-0.45 -0.3);
Change Drill 0.032;Pad '7' Octagon 0 (-0.35 -0.3);
Change Drill 0.032;Pad '8' Octagon 0 (-0.25 -0.3);
Change Drill 0.032;Pad '9' Octagon 0 (-0.15 -0.3);
Change Drill 0.032;Pad '10' Octagon 0 (-0.05 -0.3);
Change Drill 0.032;Pad '11' Octagon 0 (0.05 -0.3);
Change Drill 0.032;Pad '12' Octagon 0 (0.15 -0.3);
Change Drill 0.032;Pad '13' Octagon 0 (0.25 -0.3);
Change Drill 0.032;Pad '14' Octagon 0 (0.35 -0.3);
Change Drill 0.032;Pad '15' Octagon 0 (0.45 -0.3);
Change Drill 0.032;Pad '16' Octagon 0 (0.55 -0.3);
Change Drill 0.032;Pad '17' Octagon 0 (0.65 -0.3);
Change Drill 0.032;Pad '18' Octagon 0 (0.75 -0.3);
Change Drill 0.032;Pad '19' Octagon 0 (0.85 -0.3);
Change Drill 0.032;Pad '20' Octagon 0 (0.95 -0.3);
Change Drill 0.032;Pad '21' Octagon 0 (0.95 0.3);
Change Drill 0.032;Pad '22' Octagon 0 (0.85 0.3);
Change Drill 0.032;Pad '23' Octagon 0 (0.75 0.3);
Change Drill 0.032;Pad '24' Octagon 0 (0.65 0.3);
Change Drill 0.032;Pad '25' Octagon 0 (0.55 0.3);
Change Drill 0.032;Pad '26' Octagon 0 (0.45 0.3);
Change Drill 0.032;Pad '27' Octagon 0 (0.35 0.3);
Change Drill 0.032;Pad '28' Octagon 0 (0.25 0.3);
Change Drill 0.032;Pad '29' Octagon 0 (0.15 0.3);
Change Drill 0.032;Pad '30' Octagon 0 (0.05 0.3);
Change Drill 0.032;Pad '31' Octagon 0 (-0.05 0.3);
Change Drill 0.032;Pad '32' Octagon 0 (-0.15 0.3);
Change Drill 0.032;Pad '33' Octagon 0 (-0.25 0.3);
Change Drill 0.032;Pad '34' Octagon 0 (-0.35 0.3);
Change Drill 0.032;Pad '35' Octagon 0 (-0.45 0.3);
Change Drill 0.032;Pad '36' Octagon 0 (-0.55 0.3);
Change Drill 0.032;Pad '37' Octagon 0 (-0.65 0.3);
Change Drill 0.032;Pad '38' Octagon 0 (-0.75 0.3);
Change Drill 0.032;Pad '39' Octagon 0 (-0.85 0.3);
Change Drill 0.032;Pad '40' Octagon 0 (-0.95 0.3);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R90 (-1.055 -0.25);
Layer 21;
Wire 0.005 (-1.04 -0.05) (-1.04 -0.26);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.85 -0.088);
Layer 21;
Arc CW 0.005 (-1.04 0.05) (-1.04 -0.05) (-1.04 -0.05);
Layer 21;
Wire 0.005 (1.04 -0.26) (1.04 0.26);
Wire 0.005 (-1.04 0.26) (-1.04 0.05);
Wire 0.005 (-1.04 0.26) (1.04 0.26);
Wire 0.005 (-1.04 -0.26) (1.04 -0.26);
Edit 27128.dev;
Prefix 'U';
Package 'DIL28-6' '''''';
Value On;
Add 27128 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.VPP' '1' 'G$1.A12' '2' 'G$1.A7' '3' 'G$1.A6' '4' \
'G$1.A5' '5' 'G$1.A4' '6' 'G$1.A3' '7' 'G$1.A2' '8' \
'G$1.A1' '9' 'G$1.A0' '10' 'G$1.D0' '11' 'G$1.D1' '12' \
'G$1.D2' '13' 'G$1.D3' '15' 'G$1.D4' '16' 'G$1.D5' '17' \
'G$1.D6' '18' 'G$1.D7' '19' 'G$1.CEB' '20' 'G$1.A10' '21' \
'G$1.BEB' '22' 'G$1.A11' '23' 'G$1.A9' '24' 'G$1.A8' '25' \
'G$1.A13' '26' 'G$1.PGM' '27';
Connect 'P.GND' '14' 'P.VCC' '28';
Edit 6520.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add 6520 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.PA0' '2' 'G$1.PA1' '3' 'G$1.PA2' '4' 'G$1.PA3' '5' \
'G$1.PA4' '6' 'G$1.PA5' '7' 'G$1.PA6' '8' 'G$1.PA7' '9' \
'G$1.PB0' '10' 'G$1.PB1' '11' 'G$1.PB2' '12' 'G$1.PB3' '13' \
'G$1.PB4' '14' 'G$1.PB5' '15' 'G$1.PB6' '16' 'G$1.PB7' '17' \
'G$1.CB1' '18' 'G$1.CB2' '19' 'G$1.R/WB' '21' 'G$1.CS0' '22' \
'G$1.CS2B' '23' 'G$1.CS1' '24' 'G$1.PHI2' '25' 'G$1.D7' '26' \
'G$1.D6' '27' 'G$1.D5' '28' 'G$1.D4' '29' 'G$1.D3' '30' \
'G$1.D2' '31' 'G$1.D1' '32' 'G$1.D0' '33' 'G$1.RESB' '34' \
'G$1.A0' '35' 'G$1.A1' '36' 'G$1.IRQBB' '37' 'G$1.IRQAB' '38' \
'G$1.CA2' '39' 'G$1.CA1' '40';
Connect 'P.GND' '1' 'P.VCC' '20';
Edit 6522.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add 65C22 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.4 0.7);
Connect 'G$1.PA0' '2' 'G$1.PA1' '3' 'G$1.PA2' '4' 'G$1.PA3' '5' 'G$1.PA4' '6' \
'G$1.PA5' '7' 'G$1.PA6' '8' 'G$1.PA7' '9' 'G$1.PB0' '10' 'G$1.PB1' '11' 'G$1.PB2' '12' \
'G$1.PB3' '13' 'G$1.PB4' '14' 'G$1.PB5' '15' 'G$1.PB6' '16' 'G$1.PB7' '17' 'G$1.CA1' '40' \
'G$1.CA2' '39' 'G$1.CB1' '18' 'G$1.CB2' '19' 'G$1.PHI2' '25' 'G$1.RS0' '38' 'G$1.RS1' '37' \
'G$1.RS2' '36' 'G$1.RS3' '35' 'G$1.RESB' '34' 'G$1.D0' '33' 'G$1.D1' '32' 'G$1.D2' '31' \
'G$1.D3' '30' 'G$1.D4' '29' 'G$1.D5' '28' 'G$1.D6' '27' 'G$1.D7' '26' 'G$1.CS1' '24' \
'G$1.CS2B' '23' 'G$1.R/WB' '22' 'G$1.IRQB' '21';
Connect 'P.VCC' '20' 'P.GND' '1';
Edit 6526.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add 6526 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.4 0.7);
Connect 'G$1.PA0' '2' 'G$1.PA1' '3' 'G$1.PA2' '4' 'G$1.PA3' '5' 'G$1.PA4' '6' \
'G$1.PA5' '7' 'G$1.PA6' '8' 'G$1.PA7' '9' 'G$1.PB0' '10' 'G$1.PB1' '11' 'G$1.PB2' '12' \
'G$1.PB3' '13' 'G$1.PB4' '14' 'G$1.PB5' '15' 'G$1.PB6' '16' 'G$1.PB7' '17' 'G$1.PCB' '18' \
'G$1.TOD' '19' 'G$1.IRQB' '21' 'G$1.R/WB' '22' 'G$1.CSB' '23' 'G$1.FLAGB' '24' 'G$1.PHI2' '25' \
'G$1.D7' '26' 'G$1.D6' '27' 'G$1.D5' '28' 'G$1.D4' '29' 'G$1.D3' '30' 'G$1.D2' '31' \
'G$1.D1' '32' 'G$1.D0' '33' 'G$1.RESB' '34' 'G$1.RS3' '35' 'G$1.RS2' '36' 'G$1.RS1' '37' \
'G$1.RS0' '38' 'G$1.SP' '39' 'G$1.CNT' '40';
Connect 'P.VCC' '20' 'P.GND' '1';
Edit 6532.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add 6532 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.4 0.7);
Connect 'G$1.A5' '2' 'G$1.A4' '3' 'G$1.A3' '4' 'G$1.A2' '5' 'G$1.A1' '6' \
'G$1.A0' '7' 'G$1.PA0' '8' 'G$1.PA1' '9' 'G$1.PA2' '10' 'G$1.PA3' '11' 'G$1.PA4' '12' \
'G$1.PA5' '13' 'G$1.PA6' '14' 'G$1.PA7' '15' 'G$1.PB7' '16' 'G$1.PB6' '17' 'G$1.PB5' '18' \
'G$1.PB4' '19' 'G$1.PB3' '21' 'G$1.PB2' '22' 'G$1.PB1' '23' 'G$1.PB0' '24' 'G$1.IRQB' '25' \
'G$1.D7' '26' 'G$1.D6' '27' 'G$1.D5' '28' 'G$1.D4' '29' 'G$1.D3' '30' 'G$1.D2' '31' \
'G$1.D1' '32' 'G$1.D0' '33' 'G$1.RESB' '34' 'G$1.R/WB' '35' 'G$1.RSB' '36' 'G$1.CS2B' '37' \
'G$1.CS1' '38' 'G$1.PHI2' '39' 'G$1.A6' '40';
Connect 'P.VCC' '20' 'P.GND' '1';
Edit 6551.dev;
Prefix 'U';
Package 'DIL28-6' '''''';
Value On;
Add 65C51 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.4 0.7);
Connect 'G$1.RXCLK' '5' 'G$1.XTLI' '6' 'G$1.XTLO' '7' 'G$1.IRQ' '26' 'G$1.PHI2' '27' \
'G$1.RS0' '13' 'G$1.RS1' '14' 'G$1.R/W' '28' 'G$1.CS0' '2' 'G$1.CS1' '3' 'G$1.DSR' '17' \
'G$1.RXD' '12' 'G$1.CTS' '9' 'G$1.DCD' '16' 'G$1.TXD' '10' 'G$1.DTR' '11' 'G$1.RTS' '8' \
'G$1.D4' '22' 'G$1.D0' '18' 'G$1.D1' '19' 'G$1.D2' '20' 'G$1.D3' '21' 'G$1.D5' '23' \
'G$1.D6' '24' 'G$1.D7' '25' 'G$1.RES' '4';
Connect 'P.VCC' '15' 'P.GND' '1';
Edit 65816.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add 65C816 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.5 0.7);
Connect 'G$1.A0' '9' 'G$1.A1' '10' 'G$1.A2' '11' 'G$1.A3' '12' 'G$1.A4' '13' \
'G$1.A5' '14' 'G$1.A6' '15' 'G$1.A7' '16' 'G$1.A8' '17' 'G$1.A9' '18' 'G$1.A10' '19' \
'G$1.A11' '20' 'G$1.A12' '22' 'G$1.A13' '23' 'G$1.A14' '24' 'G$1.A15' '25' 'G$1.NMIB' '6' \
'G$1.IRQB' '4' 'G$1.BE' '36' 'G$1.D0/BA0' '33' 'G$1.D1/BA1' '32' 'G$1.D2/BA2' '31' 'G$1.D3/BA3' '30' \
'G$1.D4/BA4' '29' 'G$1.D5/BA5' '28' 'G$1.D6/BA6' '27' 'G$1.D7/BA7' '26' 'G$1.PHI2-IN' '37' 'G$1.E' '35' \
'G$1.RDY' '2' 'G$1.MLB' '5' 'G$1.M/X' '38' 'G$1.ABORTB' '3' 'G$1.VPB' '1' 'G$1.VPA' '7' \
'G$1.VDA' '39' 'G$1.R/WB' '34' 'G$1.RESB' '40';
Connect 'P.VCC' '8' 'P.GND' '21';
Edit OSROM.dev;
Prefix 'U';
Package 'DIL28-6' '''''';
Value On;
Add 27128 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.VPP' '1' 'G$1.A12' '2' 'G$1.A7' '3' 'G$1.A6' '4' \
'G$1.A5' '5' 'G$1.A4' '6' 'G$1.A3' '7' 'G$1.A2' '8' \
'G$1.A1' '9' 'G$1.A0' '10' 'G$1.D0' '11' 'G$1.D1' '12' \
'G$1.D2' '13' 'G$1.D3' '15' 'G$1.D4' '16' 'G$1.D5' '17' \
'G$1.D6' '18' 'G$1.D7' '19' 'G$1.CEB' '20' 'G$1.A10' '21' \
'G$1.BEB' '22' 'G$1.A11' '23' 'G$1.A9' '24' 'G$1.A8' '25' \
'G$1.A13' '26' 'G$1.PGM' '27';
Connect 'P.GND' '14' 'P.VCC' '28';
Edit BASROM.dev;
Prefix 'U';
Package 'DIL24-6' '''''';
Value On;
Add BASROM 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.A7' '1' 'G$1.A6' '2' 'G$1.A5' '3' 'G$1.A4' '4' \
'G$1.A3' '5' 'G$1.A2' '6' 'G$1.A1' '7' 'G$1.A0' '8' \
'G$1.D0' '9' 'G$1.D1' '10' 'G$1.D2' '11' 'G$1.D3' '13' \
'G$1.D4' '14' 'G$1.D5' '15' 'G$1.D6' '16' 'G$1.D7' '17' \
'G$1.A11' '18' 'G$1.A10' '19' 'G$1.CSB' '20' 'G$1.A12' '21' \
'G$1.A9' '22' 'G$1.A8' '23';
Connect 'P.GND' '12' 'P.VCC' '24';
Edit CO61818.dev;
Prefix 'U';
Package 'DIL20' '''''';
Value On;
Add CO61818 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.A11' '1' 'G$1.A12' '2' 'G$1.A13' '3' 'G$1.A14' '4' \
'G$1.A15' '5' 'G$1.MAPB' '6' 'G$1.RD4' '7' 'G$1.RD5' '8' \
'G$1.REN' '9' 'G$1.REFB' '11' 'G$1.S5B' '12' 'G$1.BASB' '13' \
'G$1.MPDB' '14' 'G$1.OSB' '15' 'G$1.CIB' '16' 'G$1.IOB' '17' \
'G$1.BEB' '18' 'G$1.S4B' '19';
Connect 'P.GND' '10' 'P.VCC' '20';
Edit SALLY.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add SALLYCHP 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.A0' '9' 'G$1.A1' '10' 'G$1.A2' '11' 'G$1.A3' '12' \
'G$1.A4' '13' 'G$1.A5' '14' 'G$1.A6' '15' 'G$1.A7' '16' \
'G$1.A8' '17' 'G$1.A9' '18' 'G$1.A10' '19' 'G$1.A11' '20' \
'G$1.A12' '22' 'G$1.A13' '23' 'G$1.A14' '24' 'G$1.A15' '25' \
'G$1.D0' '33' 'G$1.D1' '32' 'G$1.D2' '31' 'G$1.D3' '30' \
'G$1.D4' '29' 'G$1.D5' '28' 'G$1.D6' '27' 'G$1.D7' '26' \
'G$1.HALTB' '35' 'G$1.PHI2-IN' '37' 'G$1.PHI1' '3' 'G$1.PHI2' '39' \
'G$1.RDY' '2' 'G$1.SOB' '38' 'G$1.SYNC' '7' 'G$1.R/WB' '36' \
'G$1.NMIB' '6' 'G$1.IRQB' '4' 'G$1.RESB' '40';
Connect 'P.GND' '1' 'P.VCC' '8' 'P.GND' '21';
Edit CPU_SOCK.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add SALLYSCK 'G$1' Next 0 (0 0);
Connect 'G$1.A0' '9' 'G$1.A1' '10' 'G$1.A2' '11' 'G$1.A3' '12' \
'G$1.A4' '13' 'G$1.A5' '14' 'G$1.A6' '15' 'G$1.A7' '16' \
'G$1.A8' '17' 'G$1.A9' '18' 'G$1.A10' '19' 'G$1.A11' '20' \
'G$1.A12' '22' 'G$1.A13' '23' 'G$1.A14' '24' 'G$1.A15' '25' \
'G$1.D0' '33' 'G$1.D1' '32' 'G$1.D2' '31' 'G$1.D3' '30' \
'G$1.D4' '29' 'G$1.D5' '28' 'G$1.D6' '27' 'G$1.D7' '26' \
'G$1.HALTB' '35' 'G$1.PHI2-IN' '37' 'G$1.PHI1' '3' 'G$1.PHI2' '39' \
'G$1.RDY' '2' 'G$1.SOB' '38' 'G$1.SYNC' '7' 'G$1.R/WB' '36' \
'G$1.NMIB' '6' 'G$1.IRQB' '4' 'G$1.RESB' '40' \
'G$1.GND1' '1' 'G$1.GND2' '21' 'G$1.VCC' '8';
Edit POKEY.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add POKEY 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.D3' '2' 'G$1.D4' '3' 'G$1.D5' '4' 'G$1.D6' '5' \
'G$1.D7' '6' 'G$1.PHI2' '7' 'G$1.P6' '8' 'G$1.P7' '9' \
'G$1.P4' '10' 'G$1.P5' '11' 'G$1.P2' '12' 'G$1.P3' '13' \
'G$1.P0' '14' 'G$1.P1' '15' 'G$1.KR2B' '16' 'G$1.K5B' '18' \
'G$1.K4B' '19' 'G$1.K3B' '20' 'G$1.K2B' '21' 'G$1.K1B' '22' \
'G$1.K0B' '23' 'G$1.SID' '24' 'G$1.KR1B' '25' 'G$1.BCLK' '26' \
'G$1.ACLK' '27' 'G$1.SOD' '28' 'G$1.IRQB' '29' 'G$1.CS0B' '30' \
'G$1.CS1' '31' 'G$1.R/WB' '32' 'G$1.A3' '33' 'G$1.A2' '34' \
'G$1.A1' '35' 'G$1.A0' '36' 'G$1.AUD' '37' 'G$1.D0' '38' \
'G$1.D1' '39' 'G$1.D2' '40';
Connect 'P.GND' '1' 'P.VCC' '17';
Edit ANTIC.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add ANTIC 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.AN0' '2' 'G$1.AN1' '3' 'G$1.LPB' '4' 'G$1.AN2' '5' \
'G$1.RNMIB' '6' 'G$1.NMIB' '7' 'G$1.REFB' '8' 'G$1.HALTB' '9' \
'G$1.A3' '10' 'G$1.A2' '11' 'G$1.A1' '12' 'G$1.A0' '13' \
'G$1.R/WB' '14' 'G$1.RDY' '15' 'G$1.A10' '16' 'G$1.A12' '17' \
'G$1.A13' '18' 'G$1.A14' '19' 'G$1.A15' '20' 'G$1.A11' '22' \
'G$1.A9' '23' 'G$1.A8' '24' 'G$1.A7' '25' 'G$1.A6' '26' \
'G$1.A5' '27' 'G$1.A4' '28' 'G$1.PHI2' '29' 'G$1.D0' '30' \
'G$1.D1' '31' 'G$1.D2' '32' 'G$1.D3' '33' 'G$1.PHI0' '34' \
'G$1.FPHI0' '35' 'G$1.RESB' '36' 'G$1.D7' '37' 'G$1.D6' '38' \
'G$1.D5' '39' 'G$1.D4' '40';
Connect 'P.GND' '1' 'P.VCC' '21';
Edit GTIA.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add GTIA 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.A1' '1' 'G$1.A0' '2' 'G$1.D3' '4' 'G$1.D2' '5' \
'G$1.D1' '6' 'G$1.D0' '7' 'G$1.T0' '8' 'G$1.T1' '9' \
'G$1.T2' '10' 'G$1.T3' '11' 'G$1.S0' '12' 'G$1.S1' '13' \
'G$1.S2' '14' 'G$1.S3' '15' 'G$1.PAL' '16' 'G$1.CAD3' '17' \
'G$1.AN0' '18' 'G$1.AN1' '19' 'G$1.AN2' '20' 'G$1.COLOR' '21' \
'G$1.LUM1' '22' 'G$1.LUM2' '23' 'G$1.LUM3' '24' 'G$1.CSYNC' '25' \
'G$1.HALTB' '26' 'G$1.OSC' '28' 'G$1.FPHI0' '29' 'G$1.PHI2' '30' \
'G$1.LUM0' '31' 'G$1.CSB' '32' 'G$1.R/WB' '33' 'G$1.D7' '34' \
'G$1.D6' '35' 'G$1.D5' '36' 'G$1.D4' '37' 'G$1.A4' '38' \
'G$1.A3' '39' 'G$1.A2' '40';
Connect 'P.GND' '27' 'P.VCC' '3';
Edit AY-3-8910.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add AY-3-8910 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.NC1' '2' \
'G$1.ChB' '3' \
'G$1.ChA' '4' \
'G$1.NC2' '5' \
'G$1.IOB7' '6' \
'G$1.IOB6' '7' \
'G$1.IOB5' '8' \
'G$1.IOB4' '9' \
'G$1.IOB3' '10' \
'G$1.IOB2' '11' \
'G$1.IOB1' '12' \
'G$1.IOB0' '13' \
'G$1.IOA7' '14' \
'G$1.IOA6' '15' \
'G$1.IOA5' '16' \
'G$1.IOA4' '17' \
'G$1.IOA3' '18' \
'G$1.IOA2' '19' \
'G$1.IOA1' '20' \
'G$1.IOA0' '21' \
'G$1.CLOCK' '22' \
'G$1.RESET' '23' \
'G$1.A9' '24' \
'G$1.A8' '25' \
'G$1.TEST2' '26' \
'G$1.BDIR' '27' \
'G$1.BC2' '28' \
'G$1.BC1' '29' \
'G$1.DA7' '30' \
'G$1.DA6' '31' \
'G$1.DA5' '32' \
'G$1.DA4' '33' \
'G$1.DA3' '34' \
'G$1.DA2' '35' \
'G$1.DA1' '36' \
'G$1.DA0' '37' \
'G$1.ChC' '38' \
'G$1.TEST1' '39';
Connect 'P.GND' '1' 'P.VCC' '40';
Edit AY-3-8912.dev;
Prefix 'U';
Package 'DIL28-6' '''''';
Value On;
Add AY-3-8912 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.ChC' '1' \
'G$1.TEST1' '2' \
'G$1.ChB' '4' \
'G$1.ChA' '5' \
'G$1.IOA7' '7' \
'G$1.IOA6' '8' \
'G$1.IOA5' '9' \
'G$1.IOA4' '10' \
'G$1.IOA3' '11' \
'G$1.IOA2' '12' \
'G$1.IOA1' '13' \
'G$1.IOA0' '14' \
'G$1.CLOCK' '15' \
'G$1.RESET' '16' \
'G$1.A8' '17' \
'G$1.BDIR' '18' \
'G$1.BC2' '19' \
'G$1.BC1' '20' \
'G$1.DA7' '21' \
'G$1.DA6' '22' \
'G$1.DA5' '23' \
'G$1.DA4' '24' \
'G$1.DA3' '25' \
'G$1.DA2' '26' \
'G$1.DA1' '27' \
'G$1.DA0' '28';
Connect 'P.GND' '6' 'P.VCC' '3';
Edit AY-3-8913.dev;
Prefix 'U';
Package 'DIL24-6' '''''';
Value On;
Add AY-3-8913 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.BDIR' '2' \
'G$1.BC1' '3' \
'G$1.DA7' '4' \
'G$1.DA6' '5' \
'G$1.DA5' '6' \
'G$1.DA4' '7' \
'G$1.DA3' '8' \
'G$1.DA2' '9' \
'G$1.DA1' '10' \
'G$1.DA0' '11' \
'G$1.TESTOUT' '12' \
'G$1.TESTIN' '14' \
'G$1.ChB' '15' \
'G$1.NC' '16' \
'G$1.ChA' '17' \
'G$1.ChC' '18' \
'G$1.CLOCK' '20' \
'G$1.RESET' '21' \
'G$1.A9' '22' \
'G$1.A8' '23' \
'G$1.CS' '24';
Connect 'P.GND' '1' 'P.GND' '19' 'P.VCC' '13';
Edit YM2151.dev;
Prefix 'U';
Package 'DIL24-6' '''''';
Value On;
Add YM2151 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.IRQ' '2' \
'G$1.RESET' '3' \
'G$1.A0' '4' \
'G$1.WR' '5' \
'G$1.RD' '6' \
'G$1.CS' '7' \
'G$1.CT1' '8' \
'G$1.CT2' '9' \
'G$1.D0' '10' \
'G$1.D1' '12' \
'G$1.D2' '13' \
'G$1.D3' '14' \
'G$1.D4' '15' \
'G$1.D5' '16' \
'G$1.D6' '17' \
'G$1.D7' '18' \
'G$1.SH2' '19' \
'G$1.SH1' '20' \
'G$1.SO' '21' \
'G$1.OCLK' '23' \
'G$1.MCLK' '24';
Connect 'P.GND' '1' 'P.GND' '11' 'P.VCC' '22';
Edit YM3012.dev;
Prefix 'U';
Package 'DIL16' '''''';
Value On;
Add YM3012 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.CLK' '2' \
'G$1.DATA' '4' \
'G$1.SH2' '5' \
'G$1.SH1' '6' \
'G$1.RESET' '7' \
'G$1.A-GND1' '8' \
'G$1.CH1' '9' \
'G$1.CH2' '10' \
'G$1.COM' '11' \
'G$1.TO-BUF' '12' \
'G$1.V/2' '13' \
'G$1.BIAS+' '14' \
'G$1.BIAS-' '15' \
'G$1.A-GND2' '16';
Connect 'P.VCC' '1' 'P.GND' '3';
Edit CTS256A-AL2.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add CTS256A-AL2 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.6 0.7);
Connect 'G$1.B5/R/W' '1' \
'G$1.B7/CLOCKOUT' '2' \
'G$1.B0' '3' \
'G$1.B1' '4' \
'G$1.B2' '5' \
'G$1.A0' '6' \
'G$1.A1' '7' \
'G$1.A2' '8' \
'G$1.A3' '9' \
'G$1.A4' '10' \
'G$1.A7' '11' \
'G$1.INT3' '12' \
'G$1.INT1' '13' \
'G$1.RESET' '14' \
'G$1.A6/SCLK' '15' \
'G$1.A5/RXD' '16' \
'G$1.XTAL2/CLOCKIN' '17' \
'G$1.XTAL1' '18' \
'G$1.D7' '19' \
'G$1.D6' '20' \
'G$1.D5' '21' \
'G$1.D4' '22' \
'G$1.D3' '23' \
'G$1.D2' '24' \
'G$1.D1' '26' \
'G$1.D0' '27' \
'G$1.C0' '28' \
'G$1.C1' '29' \
'G$1.C2' '30' \
'G$1.C3' '31' \
'G$1.C4' '32' \
'G$1.C5' '33' \
'G$1.C6' '34' \
'G$1.C7' '35' \
'G$1.MC' '36' \
'G$1.B3/TXD' '37' \
'G$1.B4/ALATCH' '38' \
'G$1.B6/ENABLE' '39';
Connect 'P.GND' '40' 'P.VCC' '25';
Edit SP0256.dev;
Prefix 'U';
Package 'DIL28-6' '''''';
Value On;
Add SP0256 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.6 0.7);
Connect 'G$1.RST' '2' \
'G$1.ROMDIS' '3' \
'G$1.C1' '4' \
'G$1.C2' '5' \
'G$1.C3' '6' \
'G$1.SBY' '8' \
'G$1.LRQ' '9' \
'G$1.A8' '10' \
'G$1.A7' '11' \
'G$1.SEROUT' '12' \
'G$1.A6' '13' \
'G$1.A5' '14' \
'G$1.A4' '15' \
'G$1.A3' '16' \
'G$1.A2' '17' \
'G$1.A1' '18' \
'G$1.SE' '19' \
'G$1.ALD' '20' \
'G$1.SERIN' '21' \
'G$1.TEST' '22' \
'G$1.DIGOUT' '24' \
'G$1.SBY-RST' '25' \
'G$1.ROMCLK' '26' \
'G$1.OSC1' '27' \
'G$1.OSC2' '28';
Connect 'P.GND' '1' 'P.VCC' '7' 'P.VCC' '23';