Set Wire_Bend 2;
Grid inch 0.1 1 inch;
Layer 1 Top;
Layer 2 Route2;
Layer 3 Route3;
Layer 4 Route4;
Layer 5 Route5;
Layer 6 Route6;
Layer 7 Route7;
Layer 8 Route8;
Layer 9 Route9;
Layer 10 Route10;
Layer 11 Route11;
Layer 12 Route12;
Layer 13 Route13;
Layer 14 Route14;
Layer 15 Route15;
Layer 16 Bottom;
Layer 17 Pads;
Layer 18 Vias;
Layer 19 Unrouted;
Layer 20 Dimension;
Layer 21 tPlace;
Layer 22 bPlace;
Layer 23 tOrigins;
Layer 24 bOrigins;
Layer 25 tNames;
Layer 26 bNames;
Layer 27 tValues;
Layer 28 bValues;
Layer 29 tStop;
Layer 30 bStop;
Layer 31 tCream;
Layer 32 bCream;
Layer 33 tFinish;
Layer 34 bFinish;
Layer 35 tGlue;
Layer 36 bGlue;
Layer 37 tTest;
Layer 38 bTest;
Layer 39 tKeepout;
Layer 40 bKeepout;
Layer 41 tRestrict;
Layer 42 bRestrict;
Layer 43 vRestrict;
Layer 44 Drills;
Layer 45 Holes;
Layer 46 Milling;
Layer 47 Measures;
Layer 48 Document;
Layer 49 Reference;
Layer 91 Nets;
Layer 92 Busses;
Layer 93 Pins;
Layer 94 Symbols;
Layer 95 Names;
Layer 96 Values;
Edit OSROM.sym;
Layer 94;
Wire 0.01 (0.4 0.7) (0.4 -0.8) (-0.4 -0.8) (-0.4 0.7) \
(0.4 0.7);
Pin 'A0' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'A5' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A6' In None Middle R0 Both 0 (-0.6 0);
Pin 'A7' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A8' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A9' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A10' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A11' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A12' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'A13' In None Middle R0 Both 0 (-0.6 -0.7);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.1);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 -0.1);
Pin 'BEB' In Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'CEB' In Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'PGM' In None Middle R180 Both 0 (0.6 -0.5);
Pin 'VPP' Pwr None Middle R180 Both 0 (0.6 -0.6);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.8);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -1);
Edit BASROM.sym;
Layer 94;
Wire 0.01 (0.4 0.6) (0.4 -0.7) (-0.4 -0.7) (-0.4 0.6) \
(0.4 0.6);
Pin 'A0' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A5' In None Middle R0 Both 0 (-0.6 0);
Pin 'A6' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A7' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A8' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A9' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A10' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A11' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.1);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 -0.1);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 -0.2);
Pin 'CSB' In Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'A12' In None Middle R180 Both 0 (0.6 -0.6);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.7);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -0.9);
Edit CO61818.sym;
Layer 94;
Wire 0.01 (0.4 0.5) (0.4 -0.6) (-0.4 -0.6) (-0.4 0.5) \
(0.4 0.5);
Pin 'A11' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A12' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A13' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'A14' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A15' In None Middle R0 Both 0 (-0.6 0);
Pin 'MAPB' In Dot Middle R0 Both 0 (-0.6 -0.2);
Pin 'RD4' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'RD5' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'REN' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'S4B' Out Dot Middle R180 Both 0 (0.6 0.4);
Pin 'S5B' Out Dot Middle R180 Both 0 (0.6 0.3);
Pin 'BASB' Out Dot Middle R180 Both 0 (0.6 0.2);
Pin 'OSB' Out Dot Middle R180 Both 0 (0.6 0.1);
Pin 'CIB' Out Dot Middle R180 Both 0 (0.6 0);
Pin 'IOB' Out Dot Middle R180 Both 0 (0.6 -0.1);
Pin 'BEB' In Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'MPDB' In Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'REFB' In Dot Middle R180 Both 0 (0.6 -0.5);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 0.6);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -0.8);
Edit SALLYCHP.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' Out None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' Out None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' Out None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' Out None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' Out None Middle R0 Both 0 (-0.6 0.5);
Pin 'A5' Out None Middle R0 Both 0 (-0.6 0.4);
Pin 'A6' Out None Middle R0 Both 0 (-0.6 0.3);
Pin 'A7' Out None Middle R0 Both 0 (-0.6 0.2);
Pin 'A8' Out None Middle R0 Both 0 (-0.6 0.1);
Pin 'A9' Out None Middle R0 Both 0 (-0.6 0);
Pin 'A10' Out None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A11' Out None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A12' Out None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A13' Out None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A14' Out None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A15' Out None Middle R0 Both 0 (-0.6 -0.6);
Pin 'NMIB' In None Middle R0 Both 0 (-0.6 -0.8);
Pin 'IRQB' In None Middle R0 Both 0 (-0.6 -0.9);
Pin 'RESB' I/O Dot Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'PHI2-IN' In Clk Middle R180 Both 0 (0.6 0);
Pin 'PHI2' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'PHI1' Out None Middle R180 Both 0 (0.6 -0.2);
Pin 'HALTB' In Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'NC1' NC None Middle R180 Both 0 (0.6 -0.4);
Pin 'NC2' NC None Middle R180 Both 0 (0.6 -0.5);
Pin 'RDY' I/O None Middle R180 Both 0 (0.6 -0.7);
Pin 'SYNC' Out None Middle R180 Both 0 (0.6 -0.8);
Pin 'SOB' I/O Dot Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' Out Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -1.3);
Edit SALLYSCK.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' In None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'A5' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'A6' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'A7' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'A8' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'A9' In None Middle R0 Both 0 (-0.6 0);
Pin 'A10' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A11' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A12' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A13' In None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A14' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A15' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'NMIB' Out None Middle R0 Both 0 (-0.6 -0.8);
Pin 'IRQB' Out None Middle R0 Both 0 (-0.6 -0.9);
Pin 'RESB' I/O Dot Middle R0 Both 0 (-0.6 -1);
Pin 'VCC' Out None Middle R90 Both 0 (0 -1.3);
Pin 'GND1' Out None Middle R270 Both 0 (-0.1 1.2);
Pin 'GND2' Out None Middle R270 Both 0 (0.1 1.2);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'PHI2-IN' Out Clk Middle R180 Both 0 (0.6 0);
Pin 'PHI2' In None Middle R180 Both 0 (0.6 -0.1);
Pin 'PHI1' In None Middle R180 Both 0 (0.6 -0.2);
Pin 'HALTB' Out Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'NC1' NC None Middle R180 Both 0 (0.6 -0.4);
Pin 'NC2' NC None Middle R180 Both 0 (0.6 -0.5);
Pin 'RDY' I/O None Middle R180 Both 0 (0.6 -0.7);
Pin 'SYNC' In None Middle R180 Both 0 (0.6 -0.8);
Pin 'SOB' I/O Dot Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -1.3);
Edit PIA.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'PA0' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'PA1' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'PA2' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'PA3' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'PA4' I/O None Middle R0 Both 0 (-0.6 0.5);
Pin 'PA5' I/O None Middle R0 Both 0 (-0.6 0.4);
Pin 'PA6' I/O None Middle R0 Both 0 (-0.6 0.3);
Pin 'PA7' I/O None Middle R0 Both 0 (-0.6 0.2);
Pin 'CA1' I/O None Middle R0 Both 0 (-0.6 0.1);
Pin 'CA2' I/O None Middle R0 Both 0 (-0.6 0);
Pin 'PB0' I/O None Middle R0 Both 0 (-0.6 -0.1);
Pin 'PB1' I/O None Middle R0 Both 0 (-0.6 -0.2);
Pin 'PB2' I/O None Middle R0 Both 0 (-0.6 -0.3);
Pin 'PB3' I/O None Middle R0 Both 0 (-0.6 -0.4);
Pin 'PB4' I/O None Middle R0 Both 0 (-0.6 -0.5);
Pin 'PB5' I/O None Middle R0 Both 0 (-0.6 -0.6);
Pin 'PB6' I/O None Middle R0 Both 0 (-0.6 -0.7);
Pin 'PB7' I/O None Middle R0 Both 0 (-0.6 -0.8);
Pin 'CB1' I/O None Middle R0 Both 0 (-0.6 -0.9);
Pin 'CB2' I/O None Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'A0' Out None Middle R180 Both 0 (0.6 0);
Pin 'A1' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'IRQAB' Out Dot Middle R180 Both 0 (0.6 -0.3);
Pin 'IRQBB' Out Dot Middle R180 Both 0 (0.6 -0.4);
Pin 'RESB' In Dot Middle R180 Both 0 (0.6 -0.5);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -0.6);
Pin 'CS1' In None Middle R180 Both 0 (0.6 -0.7);
Pin 'CS2B' In Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'CS0' In None Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -1.3);
Edit POKEY.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'P0' In None Middle R0 Both 0 (-0.6 0.9);
Pin 'P1' In None Middle R0 Both 0 (-0.6 0.8);
Pin 'P2' In None Middle R0 Both 0 (-0.6 0.7);
Pin 'P3' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'P4' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'P5' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'P6' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'P7' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'KR1B' Out Dot Middle R0 Both 0 (-0.6 0);
Pin 'KR2B' Out Dot Middle R0 Both 0 (-0.6 -0.1);
Pin 'K0B' In Dot Middle R0 Both 0 (-0.6 -0.2);
Pin 'K1B' In Dot Middle R0 Both 0 (-0.6 -0.3);
Pin 'K2B' In Dot Middle R0 Both 0 (-0.6 -0.4);
Pin 'K3B' In Dot Middle R0 Both 0 (-0.6 -0.5);
Pin 'K4B' In Dot Middle R0 Both 0 (-0.6 -0.6);
Pin 'K5B' In Dot Middle R0 Both 0 (-0.6 -0.7);
Pin 'CS0B' In None Middle R0 Both 0 (-0.6 -0.9);
Pin 'CS1' In None Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'A0' I/O None Middle R180 Both 0 (0.6 0.1);
Pin 'A1' I/O None Middle R180 Both 0 (0.6 0);
Pin 'A2' I/O None Middle R180 Both 0 (0.6 -0.1);
Pin 'A3' I/O None Middle R180 Both 0 (0.6 -0.2);
Pin 'AUD' Out None Middle R180 Both 0 (0.6 -0.3);
Pin 'SID' In None Middle R180 Both 0 (0.6 -0.4);
Pin 'SOD' Out None Middle R180 Both 0 (0.6 -0.5);
Pin 'ACLK' Out Clk Middle R180 Both 0 (0.6 -0.6);
Pin 'BCLK' I/O Clk Middle R180 Both 0 (0.6 -0.7);
Pin 'IRQB' Out Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -1.3);
Edit ANTIC.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' I/O None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' I/O None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' I/O None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' I/O None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' Out None Middle R0 Both 0 (-0.6 0.5);
Pin 'A5' Out None Middle R0 Both 0 (-0.6 0.4);
Pin 'A6' Out None Middle R0 Both 0 (-0.6 0.3);
Pin 'A7' Out None Middle R0 Both 0 (-0.6 0.2);
Pin 'A8' Out None Middle R0 Both 0 (-0.6 0.1);
Pin 'A9' Out None Middle R0 Both 0 (-0.6 0);
Pin 'A10' Out None Middle R0 Both 0 (-0.6 -0.1);
Pin 'A11' Out None Middle R0 Both 0 (-0.6 -0.2);
Pin 'A12' Out None Middle R0 Both 0 (-0.6 -0.3);
Pin 'A13' Out None Middle R0 Both 0 (-0.6 -0.4);
Pin 'A14' Out None Middle R0 Both 0 (-0.6 -0.5);
Pin 'A15' Out None Middle R0 Both 0 (-0.6 -0.6);
Pin 'RNMIB' Out Dot Middle R0 Both 0 (-0.6 -0.7);
Pin 'NMIB' Out Dot Middle R0 Both 0 (-0.6 -0.8);
Pin 'HALTB' Out Dot Middle R0 Both 0 (-0.6 -0.9);
Pin 'RESB' In Dot Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'AN0' Out None Middle R180 Both 0 (0.6 0);
Pin 'AN1' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'AN2' Out None Middle R180 Both 0 (0.6 -0.2);
Pin 'FPHI0' In Clk Middle R180 Both 0 (0.6 -0.3);
Pin 'PHI2' In Clk Middle R180 Both 0 (0.6 -0.4);
Pin 'PHI0' Out Clk Middle R180 Both 0 (0.6 -0.5);
Pin 'RDY' Out None Middle R180 Both 0 (0.6 -0.6);
Pin 'REFB' Out Dot Middle R180 Both 0 (0.6 -0.7);
Pin 'R/WB' Out Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'LPB' In Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -1.3);
Edit GTIA.sym;
Layer 94;
Wire 0.01 (0.4 1) (0.4 -1.1) (-0.4 -1.1) (-0.4 1) \
(0.4 1);
Pin 'A0' In None Middle R0 Both 0 (-0.6 0.9);
Pin 'A1' In None Middle R0 Both 0 (-0.6 0.8);
Pin 'A2' In None Middle R0 Both 0 (-0.6 0.7);
Pin 'A3' In None Middle R0 Both 0 (-0.6 0.6);
Pin 'A4' In None Middle R0 Both 0 (-0.6 0.5);
Pin 'T0' In None Middle R0 Both 0 (-0.6 0.4);
Pin 'T1' In None Middle R0 Both 0 (-0.6 0.3);
Pin 'T2' In None Middle R0 Both 0 (-0.6 0.2);
Pin 'T3' In None Middle R0 Both 0 (-0.6 0.1);
Pin 'S0' In None Middle R0 Both 0 (-0.6 0);
Pin 'S1' In None Middle R0 Both 0 (-0.6 -0.1);
Pin 'S2' In None Middle R0 Both 0 (-0.6 -0.2);
Pin 'S3' In None Middle R0 Both 0 (-0.6 -0.3);
Pin 'AN0' In None Middle R0 Both 0 (-0.6 -0.5);
Pin 'AN1' In None Middle R0 Both 0 (-0.6 -0.6);
Pin 'AN2' In None Middle R0 Both 0 (-0.6 -0.7);
Pin 'OSC' In Clk Middle R0 Both 0 (-0.6 -0.8);
Pin 'FPHI0' Out Clk Middle R0 Both 0 (-0.6 -0.9);
Pin 'PHI2' In Clk Middle R0 Both 0 (-0.6 -1);
Pin 'D0' I/O None Middle R180 Both 0 (0.6 0.9);
Pin 'D1' I/O None Middle R180 Both 0 (0.6 0.8);
Pin 'D2' I/O None Middle R180 Both 0 (0.6 0.7);
Pin 'D3' I/O None Middle R180 Both 0 (0.6 0.6);
Pin 'D4' I/O None Middle R180 Both 0 (0.6 0.5);
Pin 'D5' I/O None Middle R180 Both 0 (0.6 0.4);
Pin 'D6' I/O None Middle R180 Both 0 (0.6 0.3);
Pin 'D7' I/O None Middle R180 Both 0 (0.6 0.2);
Pin 'LUM0' Out None Middle R180 Both 0 (0.6 0);
Pin 'LUM1' Out None Middle R180 Both 0 (0.6 -0.1);
Pin 'LUM2' Out None Middle R180 Both 0 (0.6 -0.2);
Pin 'LUM3' Out None Middle R180 Both 0 (0.6 -0.3);
Pin 'COLOR' Out None Middle R180 Both 0 (0.6 -0.4);
Pin 'CSYNC' Out None Middle R180 Both 0 (0.6 -0.5);
Pin 'CAD3' In None Middle R180 Both 0 (0.6 -0.6);
Pin 'CSB' In Dot Middle R180 Both 0 (0.6 -0.7);
Pin 'HALTB' In Dot Middle R180 Both 0 (0.6 -0.8);
Pin 'PAL' In Clk Middle R180 Both 0 (0.6 -0.9);
Pin 'R/WB' Out Dot Middle R180 Both 0 (0.6 -1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.4 1.1);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.4 -1.3);
Edit P.sym;
Pin 'VCC' Pwr None Middle R270 Off 0 (0 0.3);
Pin 'GND' Pwr None Middle R90 Off 0 (0 -0.3);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'GND' R0 (0.1 -0.5);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'VCC' R0 (0.1 0.4);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (0 0);
Edit P-CMOS.sym;
Pin 'VCC' Pwr None Middle R270 Off 0 (0 0.3);
Pin 'GND' Pwr None Middle R90 Off 0 (0 -0.3);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (0 0);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'VCC' R0 (0.1 0.4);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text 'GND' R0 (0.1 -0.4);
Edit DIL20.sym;
Pin '1' Pas None Short R0 Pad 0 (-0.3 0.4);
Pin '2' Pas None Short R0 Pad 0 (-0.3 0.3);
Pin '3' Pas None Short R0 Pad 0 (-0.3 0.2);
Pin '4' Pas None Short R0 Pad 0 (-0.3 0.1);
Layer 94;
Wire 0.01 (-0.2 0.45) (-0.2 -0.55) (0.2 -0.55) (0.2 0.45) \
(0.1 0.45);
Wire 0.01 (-0.2 0.45) (-0.1 0.45);
Layer 94;
Arc CCW 0.01 (-0.1 0.45) (0.1 0.45) (0.1 0.45);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.175 0.475);
Layer 96;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.175 -0.65);
Pin '5' Pas None Short R0 Pad 0 (-0.3 0);
Pin '6' Pas None Short R0 Pad 0 (-0.3 -0.1);
Pin '7' Pas None Short R0 Pad 0 (-0.3 -0.2);
Pin '8' Pas None Short R0 Pad 0 (-0.3 -0.3);
Pin '9' Pas None Short R0 Pad 0 (-0.3 -0.4);
Pin '10' Pas None Short R0 Pad 0 (-0.3 -0.5);
Pin '11' Pas None Short R180 Pad 0 (0.3 -0.5);
Pin '12' Pas None Short R180 Pad 0 (0.3 -0.4);
Pin '13' Pas None Short R180 Pad 0 (0.3 -0.3);
Pin '14' Pas None Short R180 Pad 0 (0.3 -0.2);
Pin '15' Pas None Short R180 Pad 0 (0.3 -0.1);
Pin '16' Pas None Short R180 Pad 0 (0.3 0);
Pin '17' Pas None Short R180 Pad 0 (0.3 0.1);
Pin '18' Pas None Short R180 Pad 0 (0.3 0.2);
Pin '19' Pas None Short R180 Pad 0 (0.3 0.3);
Pin '20' Pas None Short R180 Pad 0 (0.3 0.4);
Edit DIL24.sym;
Pin '1' Pas None Short R0 Pad 0 (-0.3 0.6);
Pin '2' Pas None Short R0 Pad 0 (-0.3 0.5);
Pin '3' Pas None Short R0 Pad 0 (-0.3 0.4);
Pin '4' Pas None Short R0 Pad 0 (-0.3 0.3);
Layer 94;
Wire 0.01 (-0.2 0.65) (-0.2 -0.55) (0.2 -0.55) (0.2 0.65) \
(0.1 0.65);
Wire 0.01 (-0.2 0.65) (-0.1 0.65);
Layer 94;
Arc CCW 0.01 (-0.1 0.65) (0.1 0.65) (0.1 0.65);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.175 0.675);
Layer 96;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.175 -0.65);
Pin '5' Pas None Short R0 Pad 0 (-0.3 0.2);
Pin '6' Pas None Short R0 Pad 0 (-0.3 0.1);
Pin '7' Pas None Short R0 Pad 0 (-0.3 0);
Pin '8' Pas None Short R0 Pad 0 (-0.3 -0.1);
Pin '9' Pas None Short R0 Pad 0 (-0.3 -0.2);
Pin '10' Pas None Short R0 Pad 0 (-0.3 -0.3);
Pin '11' Pas None Short R0 Pad 0 (-0.3 -0.4);
Pin '12' Pas None Short R0 Pad 0 (-0.3 -0.5);
Pin '13' Pas None Short R180 Pad 0 (0.3 -0.5);
Pin '14' Pas None Short R180 Pad 0 (0.3 -0.4);
Pin '15' Pas None Short R180 Pad 0 (0.3 -0.3);
Pin '16' Pas None Short R180 Pad 0 (0.3 -0.2);
Pin '17' Pas None Short R180 Pad 0 (0.3 -0.1);
Pin '18' Pas None Short R180 Pad 0 (0.3 0);
Pin '19' Pas None Short R180 Pad 0 (0.3 0.1);
Pin '20' Pas None Short R180 Pad 0 (0.3 0.2);
Pin '21' Pas None Short R180 Pad 0 (0.3 0.3);
Pin '22' Pas None Short R180 Pad 0 (0.3 0.4);
Pin '23' Pas None Short R180 Pad 0 (0.3 0.5);
Pin '24' Pas None Short R180 Pad 0 (0.3 0.6);
Edit DIL28.sym;
Pin '1' Pas None Short R0 Pad 0 (-0.3 0.6);
Pin '2' Pas None Short R0 Pad 0 (-0.3 0.5);
Pin '3' Pas None Short R0 Pad 0 (-0.3 0.4);
Pin '4' Pas None Short R0 Pad 0 (-0.3 0.3);
Layer 94;
Wire 0.01 (-0.2 0.65) (-0.2 -0.75) (0.2 -0.75) (0.2 0.65) \
(0.1 0.65);
Wire 0.01 (-0.2 0.65) (-0.1 0.65);
Layer 94;
Arc CCW 0.01 (-0.1 0.65) (0.1 0.65) (0.1 0.65);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.175 0.675);
Layer 96;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.175 -0.85);
Pin '5' Pas None Short R0 Pad 0 (-0.3 0.2);
Pin '6' Pas None Short R0 Pad 0 (-0.3 0.1);
Pin '7' Pas None Short R0 Pad 0 (-0.3 0);
Pin '8' Pas None Short R0 Pad 0 (-0.3 -0.1);
Pin '9' Pas None Short R0 Pad 0 (-0.3 -0.2);
Pin '10' Pas None Short R0 Pad 0 (-0.3 -0.3);
Pin '11' Pas None Short R0 Pad 0 (-0.3 -0.4);
Pin '12' Pas None Short R0 Pad 0 (-0.3 -0.5);
Pin '13' Pas None Short R0 Pad 0 (-0.3 -0.6);
Pin '14' Pas None Short R0 Pad 0 (-0.3 -0.7);
Pin '15' Pas None Short R180 Pad 0 (0.3 -0.7);
Pin '16' Pas None Short R180 Pad 0 (0.3 -0.6);
Pin '17' Pas None Short R180 Pad 0 (0.3 -0.5);
Pin '18' Pas None Short R180 Pad 0 (0.3 -0.4);
Pin '19' Pas None Short R180 Pad 0 (0.3 -0.3);
Pin '20' Pas None Short R180 Pad 0 (0.3 -0.2);
Pin '21' Pas None Short R180 Pad 0 (0.3 -0.1);
Pin '22' Pas None Short R180 Pad 0 (0.3 0);
Pin '23' Pas None Short R180 Pad 0 (0.3 0.1);
Pin '24' Pas None Short R180 Pad 0 (0.3 0.2);
Pin '25' Pas None Short R180 Pad 0 (0.3 0.3);
Pin '26' Pas None Short R180 Pad 0 (0.3 0.4);
Pin '27' Pas None Short R180 Pad 0 (0.3 0.5);
Pin '28' Pas None Short R180 Pad 0 (0.3 0.6);
Edit DIL40.sym;
Pin '1' Pas None Short R0 Pad 0 (-0.3 0.9);
Pin '2' Pas None Short R0 Pad 0 (-0.3 0.8);
Pin '3' Pas None Short R0 Pad 0 (-0.3 0.7);
Pin '4' Pas None Short R0 Pad 0 (-0.3 0.6);
Layer 94;
Wire 0.01 (-0.2 0.95) (-0.2 -1.05) (0.2 -1.05) (0.2 0.95) \
(0.1 0.95);
Wire 0.01 (-0.2 0.95) (-0.1 0.95);
Layer 94;
Arc CCW 0.01 (-0.1 0.95) (0.1 0.95) (0.1 0.95);
Layer 95;
Change Size 0.07;
Change Ratio 8;
Text '>NAME' R0 (-0.175 0.975);
Layer 96;
Change Size 0.07;
Change Ratio 8;
Text '>VALUE' R0 (-0.175 -1.15);
Pin '5' Pas None Short R0 Pad 0 (-0.3 0.5);
Pin '6' Pas None Short R0 Pad 0 (-0.3 0.4);
Pin '7' Pas None Short R0 Pad 0 (-0.3 0.3);
Pin '8' Pas None Short R0 Pad 0 (-0.3 0.2);
Pin '9' Pas None Short R0 Pad 0 (-0.3 0.1);
Pin '10' Pas None Short R0 Pad 0 (-0.3 0);
Pin '11' Pas None Short R0 Pad 0 (-0.3 -0.1);
Pin '12' Pas None Short R0 Pad 0 (-0.3 -0.2);
Pin '13' Pas None Short R0 Pad 0 (-0.3 -0.3);
Pin '14' Pas None Short R0 Pad 0 (-0.3 -0.4);
Pin '15' Pas None Short R0 Pad 0 (-0.3 -0.5);
Pin '16' Pas None Short R0 Pad 0 (-0.3 -0.6);
Pin '17' Pas None Short R0 Pad 0 (-0.3 -0.7);
Pin '18' Pas None Short R0 Pad 0 (-0.3 -0.8);
Pin '19' Pas None Short R0 Pad 0 (-0.3 -0.9);
Pin '20' Pas None Short R0 Pad 0 (-0.3 -1);
Pin '21' Pas None Short R180 Pad 0 (0.3 -1);
Pin '22' Pas None Short R180 Pad 0 (0.3 -0.9);
Pin '23' Pas None Short R180 Pad 0 (0.3 -0.8);
Pin '24' Pas None Short R180 Pad 0 (0.3 -0.7);
Pin '25' Pas None Short R180 Pad 0 (0.3 -0.6);
Pin '26' Pas None Short R180 Pad 0 (0.3 -0.5);
Pin '27' Pas None Short R180 Pad 0 (0.3 -0.4);
Pin '28' Pas None Short R180 Pad 0 (0.3 -0.3);
Pin '29' Pas None Short R180 Pad 0 (0.3 -0.2);
Pin '30' Pas None Short R180 Pad 0 (0.3 -0.1);
Pin '31' Pas None Short R180 Pad 0 (0.3 0);
Pin '32' Pas None Short R180 Pad 0 (0.3 0.1);
Pin '33' Pas None Short R180 Pad 0 (0.3 0.2);
Pin '34' Pas None Short R180 Pad 0 (0.3 0.3);
Pin '35' Pas None Short R180 Pad 0 (0.3 0.4);
Pin '36' Pas None Short R180 Pad 0 (0.3 0.5);
Pin '37' Pas None Short R180 Pad 0 (0.3 0.6);
Pin '38' Pas None Short R180 Pad 0 (0.3 0.7);
Pin '39' Pas None Short R180 Pad 0 (0.3 0.8);
Pin '40' Pas None Short R180 Pad 0 (0.3 0.9);
Edit DIL20.pac;
Description 'SOCKET DIL20';
Change Drill 0.032;Pad '1' YLongOct 0 (-0.45 -0.15);
Change Drill 0.032;Pad '2' YLongOct 0 (-0.35 -0.15);
Change Drill 0.032;Pad '3' YLongOct 0 (-0.25 -0.15);
Change Drill 0.032;Pad '4' YLongOct 0 (-0.15 -0.15);
Change Drill 0.032;Pad '5' YLongOct 0 (-0.05 -0.15);
Change Drill 0.032;Pad '6' YLongOct 0 (0.05 -0.15);
Change Drill 0.032;Pad '7' YLongOct 0 (0.15 -0.15);
Change Drill 0.032;Pad '8' YLongOct 0 (0.25 -0.15);
Change Drill 0.032;Pad '9' YLongOct 0 (0.35 -0.15);
Change Drill 0.032;Pad '10' YLongOct 0 (0.45 -0.15);
Change Drill 0.032;Pad '11' YLongOct 0 (0.45 0.15);
Change Drill 0.032;Pad '12' YLongOct 0 (0.35 0.15);
Change Drill 0.032;Pad '13' YLongOct 0 (0.25 0.15);
Change Drill 0.032;Pad '14' YLongOct 0 (0.15 0.15);
Change Drill 0.032;Pad '15' YLongOct 0 (0.05 0.15);
Change Drill 0.032;Pad '16' YLongOct 0 (-0.05 0.15);
Change Drill 0.032;Pad '17' YLongOct 0 (-0.15 0.15);
Change Drill 0.032;Pad '18' YLongOct 0 (-0.25 0.15);
Change Drill 0.032;Pad '19' YLongOct 0 (-0.35 0.15);
Change Drill 0.032;Pad '20' YLongOct 0 (-0.45 0.15);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R90 (-0.507 -0.105);
Layer 21;
Wire 0.005 (-0.495 -0.025) (-0.495 -0.11);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.41 -0.035);
Layer 21;
Arc CCW 0.005 (-0.495 -0.025) (-0.495 0.025) (-0.495 0.025);
Layer 21;
Wire 0.005 (0.495 -0.11) (0.495 0.11);
Wire 0.005 (0.495 -0.11) (-0.495 -0.11);
Wire 0.005 (-0.495 0.11) (-0.495 0.025);
Wire 0.005 (-0.495 0.11) (0.495 0.11);
Edit DIL24-6.pac;
Description 'SOCKET DIL24, 0.6 inch';
Change Drill 0.032;Pad '1' YLongOct 0 (-0.55 -0.3);
Change Drill 0.032;Pad '2' YLongOct 0 (-0.45 -0.3);
Change Drill 0.032;Pad '3' YLongOct 0 (-0.35 -0.3);
Change Drill 0.032;Pad '4' YLongOct 0 (-0.25 -0.3);
Change Drill 0.032;Pad '5' YLongOct 0 (-0.15 -0.3);
Change Drill 0.032;Pad '6' YLongOct 0 (-0.05 -0.3);
Change Drill 0.032;Pad '7' YLongOct 0 (0.05 -0.3);
Change Drill 0.032;Pad '8' YLongOct 0 (0.15 -0.3);
Change Drill 0.032;Pad '9' YLongOct 0 (0.25 -0.3);
Change Drill 0.032;Pad '10' YLongOct 0 (0.35 -0.3);
Change Drill 0.032;Pad '11' YLongOct 0 (0.45 -0.3);
Change Drill 0.032;Pad '12' YLongOct 0 (0.55 -0.3);
Change Drill 0.032;Pad '13' YLongOct 0 (0.55 0.3);
Change Drill 0.032;Pad '14' YLongOct 0 (0.45 0.3);
Change Drill 0.032;Pad '15' YLongOct 0 (0.35 0.3);
Change Drill 0.032;Pad '16' YLongOct 0 (0.25 0.3);
Change Drill 0.032;Pad '17' YLongOct 0 (0.15 0.3);
Change Drill 0.032;Pad '18' YLongOct 0 (0.05 0.3);
Change Drill 0.032;Pad '19' YLongOct 0 (-0.05 0.3);
Change Drill 0.032;Pad '20' YLongOct 0 (-0.15 0.3);
Change Drill 0.032;Pad '21' YLongOct 0 (-0.25 0.3);
Change Drill 0.032;Pad '22' YLongOct 0 (-0.35 0.3);
Change Drill 0.032;Pad '23' YLongOct 0 (-0.45 0.3);
Change Drill 0.032;Pad '24' YLongOct 0 (-0.55 0.3);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R0 (-0.45 0.015);
Layer 21;
Wire 0.005 (-0.595 -0.05) (-0.595 -0.26);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '1' R90 (-0.525 -0.238);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '24' R90 (-0.525 0.162);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '12' R90 (0.575 -0.238);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '13' R90 (0.575 0.162);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.45 -0.085);
Layer 21;
Arc CW 0.005 (-0.595 0.05) (-0.595 -0.05) (-0.595 -0.05);
Layer 21;
Wire 0.005 (0.595 -0.26) (0.595 0.26);
Wire 0.005 (-0.595 0.26) (-0.595 0.05);
Wire 0.005 (-0.595 0.26) (0.595 0.26);
Wire 0.005 (-0.595 -0.26) (0.595 -0.26);
Edit DIL28-6.pac;
Description 'SOCKET DIL28, 0.6 inch';
Change Drill 0.032;Pad '1' YLongOct 0 (-0.65 -0.3);
Change Drill 0.032;Pad '2' YLongOct 0 (-0.55 -0.3);
Change Drill 0.032;Pad '3' YLongOct 0 (-0.45 -0.3);
Change Drill 0.032;Pad '4' YLongOct 0 (-0.35 -0.3);
Change Drill 0.032;Pad '5' YLongOct 0 (-0.25 -0.3);
Change Drill 0.032;Pad '6' YLongOct 0 (-0.15 -0.3);
Change Drill 0.032;Pad '7' YLongOct 0 (-0.05 -0.3);
Change Drill 0.032;Pad '8' YLongOct 0 (0.05 -0.3);
Change Drill 0.032;Pad '9' YLongOct 0 (0.15 -0.3);
Change Drill 0.032;Pad '10' YLongOct 0 (0.25 -0.3);
Change Drill 0.032;Pad '11' YLongOct 0 (0.35 -0.3);
Change Drill 0.032;Pad '12' YLongOct 0 (0.45 -0.3);
Change Drill 0.032;Pad '13' YLongOct 0 (0.55 -0.3);
Change Drill 0.032;Pad '14' YLongOct 0 (0.65 -0.3);
Change Drill 0.032;Pad '15' YLongOct 0 (0.65 0.3);
Change Drill 0.032;Pad '16' YLongOct 0 (0.55 0.3);
Change Drill 0.032;Pad '17' YLongOct 0 (0.45 0.3);
Change Drill 0.032;Pad '18' YLongOct 0 (0.35 0.3);
Change Drill 0.032;Pad '19' YLongOct 0 (0.25 0.3);
Change Drill 0.032;Pad '20' YLongOct 0 (0.15 0.3);
Change Drill 0.032;Pad '21' YLongOct 0 (0.05 0.3);
Change Drill 0.032;Pad '22' YLongOct 0 (-0.05 0.3);
Change Drill 0.032;Pad '23' YLongOct 0 (-0.15 0.3);
Change Drill 0.032;Pad '24' YLongOct 0 (-0.25 0.3);
Change Drill 0.032;Pad '25' YLongOct 0 (-0.35 0.3);
Change Drill 0.032;Pad '26' YLongOct 0 (-0.45 0.3);
Change Drill 0.032;Pad '27' YLongOct 0 (-0.55 0.3);
Change Drill 0.032;Pad '28' YLongOct 0 (-0.65 0.3);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R0 (-0.55 0.025);
Layer 21;
Wire 0.005 (-0.695 -0.05) (-0.695 -0.26);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '1' R90 (-0.625 -0.237);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '28' R90 (-0.625 0.151);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '14' R90 (0.675 -0.238);
Layer 21;
Change Size 0.05;
Change Ratio 10;
Text '15' R90 (0.675 0.162);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.55 -0.087);
Layer 21;
Arc CW 0.005 (-0.695 0.05) (-0.695 -0.05) (-0.695 -0.05);
Layer 21;
Wire 0.005 (0.695 -0.26) (0.695 0.26);
Wire 0.005 (-0.695 0.26) (-0.695 0.05);
Wire 0.005 (-0.695 0.26) (0.695 0.26);
Wire 0.005 (-0.695 -0.26) (0.695 -0.26);
Edit DIL40.pac;
Description 'SOCKET DIL40';
Change Drill 0.032;Pad '1' YLongOct 0 (-0.95 -0.3);
Change Drill 0.032;Pad '2' YLongOct 0 (-0.85 -0.3);
Change Drill 0.032;Pad '3' YLongOct 0 (-0.75 -0.3);
Change Drill 0.032;Pad '4' YLongOct 0 (-0.65 -0.3);
Change Drill 0.032;Pad '5' YLongOct 0 (-0.55 -0.3);
Change Drill 0.032;Pad '6' YLongOct 0 (-0.45 -0.3);
Change Drill 0.032;Pad '7' YLongOct 0 (-0.35 -0.3);
Change Drill 0.032;Pad '8' YLongOct 0 (-0.25 -0.3);
Change Drill 0.032;Pad '9' YLongOct 0 (-0.15 -0.3);
Change Drill 0.032;Pad '10' YLongOct 0 (-0.05 -0.3);
Change Drill 0.032;Pad '11' YLongOct 0 (0.05 -0.3);
Change Drill 0.032;Pad '12' YLongOct 0 (0.15 -0.3);
Change Drill 0.032;Pad '13' YLongOct 0 (0.25 -0.3);
Change Drill 0.032;Pad '14' YLongOct 0 (0.35 -0.3);
Change Drill 0.032;Pad '15' YLongOct 0 (0.45 -0.3);
Change Drill 0.032;Pad '16' YLongOct 0 (0.55 -0.3);
Change Drill 0.032;Pad '17' YLongOct 0 (0.65 -0.3);
Change Drill 0.032;Pad '18' YLongOct 0 (0.75 -0.3);
Change Drill 0.032;Pad '19' YLongOct 0 (0.85 -0.3);
Change Drill 0.032;Pad '20' YLongOct 0 (0.95 -0.3);
Change Drill 0.032;Pad '21' YLongOct 0 (0.95 0.3);
Change Drill 0.032;Pad '22' YLongOct 0 (0.85 0.3);
Change Drill 0.032;Pad '23' YLongOct 0 (0.75 0.3);
Change Drill 0.032;Pad '24' YLongOct 0 (0.65 0.3);
Change Drill 0.032;Pad '25' YLongOct 0 (0.55 0.3);
Change Drill 0.032;Pad '26' YLongOct 0 (0.45 0.3);
Change Drill 0.032;Pad '27' YLongOct 0 (0.35 0.3);
Change Drill 0.032;Pad '28' YLongOct 0 (0.25 0.3);
Change Drill 0.032;Pad '29' YLongOct 0 (0.15 0.3);
Change Drill 0.032;Pad '30' YLongOct 0 (0.05 0.3);
Change Drill 0.032;Pad '31' YLongOct 0 (-0.05 0.3);
Change Drill 0.032;Pad '32' YLongOct 0 (-0.15 0.3);
Change Drill 0.032;Pad '33' YLongOct 0 (-0.25 0.3);
Change Drill 0.032;Pad '34' YLongOct 0 (-0.35 0.3);
Change Drill 0.032;Pad '35' YLongOct 0 (-0.45 0.3);
Change Drill 0.032;Pad '36' YLongOct 0 (-0.55 0.3);
Change Drill 0.032;Pad '37' YLongOct 0 (-0.65 0.3);
Change Drill 0.032;Pad '38' YLongOct 0 (-0.75 0.3);
Change Drill 0.032;Pad '39' YLongOct 0 (-0.85 0.3);
Change Drill 0.032;Pad '40' YLongOct 0 (-0.95 0.3);
Layer 25;
Change Size 0.07;
Change Ratio 10;
Text '>NAME' R90 (-1.055 -0.25);
Layer 21;
Wire 0.005 (-1.04 -0.05) (-1.04 -0.26);
Layer 27;
Change Size 0.07;
Change Ratio 10;
Text '>VALUE' R0 (-0.85 -0.088);
Layer 21;
Arc CW 0.005 (-1.04 0.05) (-1.04 -0.05) (-1.04 -0.05);
Layer 21;
Wire 0.005 (1.04 -0.26) (1.04 0.26);
Wire 0.005 (-1.04 0.26) (-1.04 0.05);
Wire 0.005 (-1.04 0.26) (1.04 0.26);
Wire 0.005 (-1.04 -0.26) (1.04 -0.26);
Edit DIL20.dev;
Prefix 'IC';
Description 'SOCKET DIL20';
Value On;
Add DIL20 'G$1' Next 0 (0 0);
Package 'DIL20' '''''';
Technology '';
Connect 'G$1.1' '1' 'G$1.2' '2' 'G$1.3' '3' 'G$1.4' '4' 'G$1.5' '5' \
'G$1.6' '6' 'G$1.7' '7' 'G$1.8' '8' 'G$1.9' '9' 'G$1.10' '10' 'G$1.11' '11' \
'G$1.12' '12' 'G$1.13' '13' 'G$1.14' '14' 'G$1.15' '15' 'G$1.16' '16' 'G$1.17' '17' \
'G$1.18' '18' 'G$1.19' '19' 'G$1.20' '20';
Edit DIL24.dev;
Prefix 'IC';
Description 'SOCKET DIL24';
Value On;
Add DIL24 'G$1' Next 0 (0 0);
Package 'DIL24-6' '''''';
Technology '';
Connect 'G$1.1' '1' 'G$1.2' '2' 'G$1.3' '3' 'G$1.4' '4' 'G$1.5' '5' \
'G$1.6' '6' 'G$1.7' '7' 'G$1.8' '8' 'G$1.9' '9' 'G$1.10' '10' 'G$1.11' '11' \
'G$1.12' '12' 'G$1.13' '13' 'G$1.14' '14' 'G$1.15' '15' 'G$1.16' '16' 'G$1.17' '17' \
'G$1.18' '18' 'G$1.19' '19' 'G$1.20' '20' 'G$1.21' '21' 'G$1.22' '22' 'G$1.23' '23' \
'G$1.24' '24';
Package 'DIL24-6' '/6';
Technology '';
Connect 'G$1.1' '1' 'G$1.2' '2' 'G$1.3' '3' 'G$1.4' '4' 'G$1.5' '5' \
'G$1.6' '6' 'G$1.7' '7' 'G$1.8' '8' 'G$1.9' '9' 'G$1.10' '10' 'G$1.11' '11' \
'G$1.12' '12' 'G$1.13' '13' 'G$1.14' '14' 'G$1.15' '15' 'G$1.16' '16' 'G$1.17' '17' \
'G$1.18' '18' 'G$1.19' '19' 'G$1.20' '20' 'G$1.21' '21' 'G$1.22' '22' 'G$1.23' '23' \
'G$1.24' '24';
Edit DIL28.dev;
Prefix 'IC';
Description 'SOCKET DIL28';
Value On;
Add DIL28 'G$1' Next 0 (0 0);
Package 'DIL28-6' '''''';
Technology '';
Connect 'G$1.1' '1' 'G$1.2' '2' 'G$1.3' '3' 'G$1.4' '4' 'G$1.5' '5' \
'G$1.6' '6' 'G$1.7' '7' 'G$1.8' '8' 'G$1.9' '9' 'G$1.10' '10' 'G$1.11' '11' \
'G$1.12' '12' 'G$1.13' '13' 'G$1.14' '14' 'G$1.15' '15' 'G$1.16' '16' 'G$1.17' '17' \
'G$1.18' '18' 'G$1.19' '19' 'G$1.20' '20' 'G$1.21' '21' 'G$1.22' '22' 'G$1.23' '23' \
'G$1.24' '24' 'G$1.25' '25' 'G$1.26' '26' 'G$1.27' '27' 'G$1.28' '28';
Edit DIL40.dev;
Prefix 'IC';
Description 'SOCKET DIL40';
Value On;
Add DIL40 'G$1' Next 0 (0 0);
Package 'DIL40' '''''';
Technology '';
Connect 'G$1.1' '1' 'G$1.2' '2' 'G$1.3' '3' 'G$1.4' '4' 'G$1.5' '5' \
'G$1.6' '6' 'G$1.7' '7' 'G$1.8' '8' 'G$1.9' '9' 'G$1.10' '10' 'G$1.11' '11' \
'G$1.12' '12' 'G$1.13' '13' 'G$1.14' '14' 'G$1.15' '15' 'G$1.16' '16' 'G$1.17' '17' \
'G$1.18' '18' 'G$1.19' '19' 'G$1.20' '20' 'G$1.21' '21' 'G$1.22' '22' 'G$1.23' '23' \
'G$1.24' '24' 'G$1.25' '25' 'G$1.26' '26' 'G$1.27' '27' 'G$1.28' '28' 'G$1.29' '29' \
'G$1.30' '30' 'G$1.31' '31' 'G$1.32' '32' 'G$1.33' '33' 'G$1.34' '34' 'G$1.35' '35' \
'G$1.36' '36' 'G$1.37' '37' 'G$1.38' '38' 'G$1.39' '39' 'G$1.40' '40';
Edit OSROM.dev;
Prefix 'U';
Package 'DIL28-6' '''''';
Value On;
Add OSROM 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.VPP' '1' 'G$1.A12' '2' 'G$1.A7' '3' 'G$1.A6' '4' \
'G$1.A5' '5' 'G$1.A4' '6' 'G$1.A3' '7' 'G$1.A2' '8' \
'G$1.A1' '9' 'G$1.A0' '10' 'G$1.D0' '11' 'G$1.D1' '12' \
'G$1.D2' '13' 'G$1.D3' '15' 'G$1.D4' '16' 'G$1.D5' '17' \
'G$1.D6' '18' 'G$1.D7' '19' 'G$1.CEB' '20' 'G$1.A10' '21' \
'G$1.BEB' '22' 'G$1.A11' '23' 'G$1.A9' '24' 'G$1.A8' '25' \
'G$1.A13' '26' 'G$1.PGM' '27';
Connect 'P.GND' '14' 'P.VCC' '28';
Edit BASROM.dev;
Prefix 'U';
Package 'DIL24-6' '''''';
Value On;
Add BASROM 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.A7' '1' 'G$1.A6' '2' 'G$1.A5' '3' 'G$1.A4' '4' \
'G$1.A3' '5' 'G$1.A2' '6' 'G$1.A1' '7' 'G$1.A0' '8' \
'G$1.D0' '9' 'G$1.D1' '10' 'G$1.D2' '11' 'G$1.D3' '13' \
'G$1.D4' '14' 'G$1.D5' '15' 'G$1.D6' '16' 'G$1.D7' '17' \
'G$1.A11' '18' 'G$1.A10' '19' 'G$1.CSB' '20' 'G$1.A12' '21' \
'G$1.A9' '22' 'G$1.A8' '23';
Connect 'P.GND' '12' 'P.VCC' '24';
Edit CO61818.dev;
Prefix 'U';
Package 'DIL20' '''''';
Value On;
Add CO61818 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.A11' '1' 'G$1.A12' '2' 'G$1.A13' '3' 'G$1.A14' '4' \
'G$1.A15' '5' 'G$1.MAPB' '6' 'G$1.RD4' '7' 'G$1.RD5' '8' \
'G$1.REN' '9' 'G$1.REFB' '11' 'G$1.S5B' '12' 'G$1.BASB' '13' \
'G$1.MPDB' '14' 'G$1.OSB' '15' 'G$1.CIB' '16' 'G$1.IOB' '17' \
'G$1.BEB' '18' 'G$1.S4B' '19';
Connect 'P.GND' '10' 'P.VCC' '20';
Edit SALLY.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add SALLYCHP 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.A0' '9' 'G$1.A1' '10' 'G$1.A2' '11' 'G$1.A3' '12' \
'G$1.A4' '13' 'G$1.A5' '14' 'G$1.A6' '15' 'G$1.A7' '16' \
'G$1.A8' '17' 'G$1.A9' '18' 'G$1.A10' '19' 'G$1.A11' '20' \
'G$1.A12' '22' 'G$1.A13' '23' 'G$1.A14' '24' 'G$1.A15' '25' \
'G$1.D0' '33' 'G$1.D1' '32' 'G$1.D2' '31' 'G$1.D3' '30' \
'G$1.D4' '29' 'G$1.D5' '28' 'G$1.D6' '27' 'G$1.D7' '26' \
'G$1.HALTB' '35' 'G$1.PHI2-IN' '37' 'G$1.PHI1' '3' 'G$1.PHI2' '39' \
'G$1.RDY' '2' 'G$1.SOB' '38' 'G$1.SYNC' '7' 'G$1.R/WB' '36' \
'G$1.NMIB' '6' 'G$1.IRQB' '4' 'G$1.RESB' '40';
Connect 'P.GND' '1' 'P.VCC' '8' 'P.GND' '21';
Edit CPU_SOCK.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add SALLYSCK 'G$1' Next 0 (0 0);
Connect 'G$1.A0' '9' 'G$1.A1' '10' 'G$1.A2' '11' 'G$1.A3' '12' \
'G$1.A4' '13' 'G$1.A5' '14' 'G$1.A6' '15' 'G$1.A7' '16' \
'G$1.A8' '17' 'G$1.A9' '18' 'G$1.A10' '19' 'G$1.A11' '20' \
'G$1.A12' '22' 'G$1.A13' '23' 'G$1.A14' '24' 'G$1.A15' '25' \
'G$1.D0' '33' 'G$1.D1' '32' 'G$1.D2' '31' 'G$1.D3' '30' \
'G$1.D4' '29' 'G$1.D5' '28' 'G$1.D6' '27' 'G$1.D7' '26' \
'G$1.HALTB' '35' 'G$1.PHI2-IN' '37' 'G$1.PHI1' '3' 'G$1.PHI2' '39' \
'G$1.RDY' '2' 'G$1.SOB' '38' 'G$1.SYNC' '7' 'G$1.R/WB' '36' \
'G$1.NMIB' '6' 'G$1.IRQB' '4' 'G$1.RESB' '40' \
'G$1.GND1' '1' 'G$1.GND2' '21' 'G$1.VCC' '8';
Edit PIA.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add PIA 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.PA0' '2' 'G$1.PA1' '3' 'G$1.PA2' '4' 'G$1.PA3' '5' \
'G$1.PA4' '6' 'G$1.PA5' '7' 'G$1.PA6' '8' 'G$1.PA7' '9' \
'G$1.PB0' '10' 'G$1.PB1' '11' 'G$1.PB2' '12' 'G$1.PB3' '13' \
'G$1.PB4' '14' 'G$1.PB5' '15' 'G$1.PB6' '16' 'G$1.PB7' '17' \
'G$1.CB1' '18' 'G$1.CB2' '19' 'G$1.R/WB' '21' 'G$1.CS0' '22' \
'G$1.CS2B' '23' 'G$1.CS1' '24' 'G$1.PHI2' '25' 'G$1.D7' '26' \
'G$1.D6' '27' 'G$1.D5' '28' 'G$1.D4' '29' 'G$1.D3' '30' \
'G$1.D2' '31' 'G$1.D1' '32' 'G$1.D0' '33' 'G$1.RESB' '34' \
'G$1.A0' '35' 'G$1.A1' '36' 'G$1.IRQBB' '37' 'G$1.IRQAB' '38' \
'G$1.CA2' '39' 'G$1.CA1' '40';
Connect 'P.GND' '1' 'P.VCC' '20';
Edit POKEY.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add POKEY 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.D3' '2' 'G$1.D4' '3' 'G$1.D5' '4' 'G$1.D6' '5' \
'G$1.D7' '6' 'G$1.PHI2' '7' 'G$1.P6' '8' 'G$1.P7' '9' \
'G$1.P4' '10' 'G$1.P5' '11' 'G$1.P2' '12' 'G$1.P3' '13' \
'G$1.P0' '14' 'G$1.P1' '15' 'G$1.KR2B' '16' 'G$1.K5B' '18' \
'G$1.K4B' '19' 'G$1.K3B' '20' 'G$1.K2B' '21' 'G$1.K1B' '22' \
'G$1.K0B' '23' 'G$1.SID' '24' 'G$1.KR1B' '25' 'G$1.BCLK' '26' \
'G$1.ACLK' '27' 'G$1.SOD' '28' 'G$1.IRQB' '29' 'G$1.CS0B' '30' \
'G$1.CS1' '31' 'G$1.R/WB' '32' 'G$1.A3' '33' 'G$1.A2' '34' \
'G$1.A1' '35' 'G$1.A0' '36' 'G$1.AUD' '37' 'G$1.D0' '38' \
'G$1.D1' '39' 'G$1.D2' '40';
Connect 'P.GND' '1' 'P.VCC' '17';
Edit ANTIC.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add ANTIC 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.AN0' '2' 'G$1.AN1' '3' 'G$1.LPB' '4' 'G$1.AN2' '5' \
'G$1.RNMIB' '6' 'G$1.NMIB' '7' 'G$1.REFB' '8' 'G$1.HALTB' '9' \
'G$1.A3' '10' 'G$1.A2' '11' 'G$1.A1' '12' 'G$1.A0' '13' \
'G$1.R/WB' '14' 'G$1.RDY' '15' 'G$1.A10' '16' 'G$1.A12' '17' \
'G$1.A13' '18' 'G$1.A14' '19' 'G$1.A15' '20' 'G$1.A11' '22' \
'G$1.A9' '23' 'G$1.A8' '24' 'G$1.A7' '25' 'G$1.A6' '26' \
'G$1.A5' '27' 'G$1.A4' '28' 'G$1.PHI2' '29' 'G$1.D0' '30' \
'G$1.D1' '31' 'G$1.D2' '32' 'G$1.D3' '33' 'G$1.PHI0' '34' \
'G$1.FPHI0' '35' 'G$1.RESB' '36' 'G$1.D7' '37' 'G$1.D6' '38' \
'G$1.D5' '39' 'G$1.D4' '40';
Connect 'P.GND' '1' 'P.VCC' '21';
Edit GTIA.dev;
Prefix 'U';
Package 'DIL40' '''''';
Value On;
Add GTIA 'G$1' Next 0 (0 0);
Add P-CMOS 'P' Request 0 (-1.2 0.7);
Connect 'G$1.A1' '1' 'G$1.A0' '2' 'G$1.D3' '4' 'G$1.D2' '5' \
'G$1.D1' '6' 'G$1.D0' '7' 'G$1.T0' '8' 'G$1.T1' '9' \
'G$1.T2' '10' 'G$1.T3' '11' 'G$1.S0' '12' 'G$1.S1' '13' \
'G$1.S2' '14' 'G$1.S3' '15' 'G$1.PAL' '16' 'G$1.CAD3' '17' \
'G$1.AN0' '18' 'G$1.AN1' '19' 'G$1.AN2' '20' 'G$1.COLOR' '21' \
'G$1.LUM1' '22' 'G$1.LUM2' '23' 'G$1.LUM3' '24' 'G$1.CSYNC' '25' \
'G$1.HALTB' '26' 'G$1.OSC' '28' 'G$1.FPHI0' '29' 'G$1.PHI2' '30' \
'G$1.LUM0' '31' 'G$1.CSB' '32' 'G$1.R/WB' '33' 'G$1.D7' '34' \
'G$1.D6' '35' 'G$1.D5' '36' 'G$1.D4' '37' 'G$1.A4' '38' \
'G$1.A3' '39' 'G$1.A2' '40';
Connect 'P.GND' '27' 'P.VCC' '3';